Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove

Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove extra core counts in cluster 2 and 3

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feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.co

feat(ti): remove extra core counts in cluster 2 and 3

No K3 SoC supported by this TARGET_BOARD has any cluster
2 or 3 cores. Remove these to save some memory.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I27868a2f3aac25fa0fdec56847e273d88f0d9a87

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Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function

Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

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refactor(ti): factor out common board code into common files

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c9f200b3d

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Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our ma

Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table

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plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0

ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfo

plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0

ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfortunately does cause confusion while reading the code, so, lets
make things explicit by selecting 0x0 as the "SEC_SRAM_BASE" out of
which we compute the BL31_BASE depending on usage.

Lets also document a warning while at it to help folks copying code
over to a custom K3 platform and optimizing size by disabling PIE to
modify the defaults.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8e67a9210e907e266ff6a78ba4d02e3259bb2b21

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plat: ti: k3: board: Lets cast our macros

Lets cast our macros to the right types and reduce a few MISRA
warnings.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca063509

plat: ti: k3: board: Lets cast our macros

Lets cast our macros to the right types and reduce a few MISRA
warnings.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c

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Merge changes from topic "ti-cluster-power" into integration

* changes:
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
ti: k3: drivers: ti_sci: Remove indirect structure of cons

Merge changes from topic "ti-cluster-power" into integration

* changes:
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
ti: k3: drivers: ti_sci: Remove indirect structure of const data
ti: k3: common: Enable ARM cluster power down
ti: k3: common: Rename device IDs to be more consistent

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ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sendi

ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216

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Merge "ti: Unify Platform specific defines for PSCI module" into integration

ti: Unify Platform specific defines for PSCI module

PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUS

ti: Unify Platform specific defines for PSCI module

PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ia7072d82116b03904c1b3982f37d96347203e621

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Merge "ti: k3: common: Remove MSMC port definitions" into integration

ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by d

ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by defined the number of cores on that port to zero.
This simplifies several code paths, do this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1514 from glneo/for-upstream-psci

K3 PSCI Support

ti: k3: common: Add basic PSCI core on support

Use TI-SCI messages to request core start from system controller
firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>

Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>

PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1403 from glneo/for-upstream-k3

TI K3 platform support

ti: k3: Introduce basic generic board support

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined co

ti: k3: Introduce basic generic board support

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined configuration to begin with.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

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