1*db77f8bfSYann Gautier /* 2*db77f8bfSYann Gautier * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3*db77f8bfSYann Gautier * 4*db77f8bfSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*db77f8bfSYann Gautier */ 6*db77f8bfSYann Gautier 7*db77f8bfSYann Gautier #include <assert.h> 8*db77f8bfSYann Gautier 9*db77f8bfSYann Gautier #include <lib/xlat_tables/xlat_tables_v2.h> 10*db77f8bfSYann Gautier 11*db77f8bfSYann Gautier #include <platform_def.h> 12*db77f8bfSYann Gautier 13*db77f8bfSYann Gautier #define BKPR_BOOT_MODE 96U 14*db77f8bfSYann Gautier 15*db77f8bfSYann Gautier #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 16*db77f8bfSYann Gautier STM32MP_SYSRAM_SIZE, \ 17*db77f8bfSYann Gautier MT_MEMORY | \ 18*db77f8bfSYann Gautier MT_RW | \ 19*db77f8bfSYann Gautier MT_SECURE | \ 20*db77f8bfSYann Gautier MT_EXECUTE_NEVER) 21*db77f8bfSYann Gautier 22*db77f8bfSYann Gautier #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 23*db77f8bfSYann Gautier STM32MP_DEVICE_SIZE, \ 24*db77f8bfSYann Gautier MT_DEVICE | \ 25*db77f8bfSYann Gautier MT_RW | \ 26*db77f8bfSYann Gautier MT_SECURE | \ 27*db77f8bfSYann Gautier MT_EXECUTE_NEVER) 28*db77f8bfSYann Gautier 29*db77f8bfSYann Gautier #if defined(IMAGE_BL2) 30*db77f8bfSYann Gautier static const mmap_region_t stm32mp2_mmap[] = { 31*db77f8bfSYann Gautier MAP_SYSRAM, 32*db77f8bfSYann Gautier MAP_DEVICE, 33*db77f8bfSYann Gautier {0} 34*db77f8bfSYann Gautier }; 35*db77f8bfSYann Gautier #endif 36*db77f8bfSYann Gautier 37*db77f8bfSYann Gautier void configure_mmu(void) 38*db77f8bfSYann Gautier { 39*db77f8bfSYann Gautier mmap_add(stm32mp2_mmap); 40*db77f8bfSYann Gautier init_xlat_tables(); 41*db77f8bfSYann Gautier 42*db77f8bfSYann Gautier enable_mmu_el3(0); 43*db77f8bfSYann Gautier } 44*db77f8bfSYann Gautier 45*db77f8bfSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 46*db77f8bfSYann Gautier { 47*db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 48*db77f8bfSYann Gautier return GPIOZ_BASE; 49*db77f8bfSYann Gautier } 50*db77f8bfSYann Gautier 51*db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 52*db77f8bfSYann Gautier 53*db77f8bfSYann Gautier return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 54*db77f8bfSYann Gautier } 55*db77f8bfSYann Gautier 56*db77f8bfSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 57*db77f8bfSYann Gautier { 58*db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 59*db77f8bfSYann Gautier return 0; 60*db77f8bfSYann Gautier } 61*db77f8bfSYann Gautier 62*db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 63*db77f8bfSYann Gautier 64*db77f8bfSYann Gautier return bank * GPIO_BANK_OFFSET; 65*db77f8bfSYann Gautier } 66*db77f8bfSYann Gautier 67*db77f8bfSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 68*db77f8bfSYann Gautier { 69*db77f8bfSYann Gautier if (bank == GPIO_BANK_Z) { 70*db77f8bfSYann Gautier return CK_BUS_GPIOZ; 71*db77f8bfSYann Gautier } 72*db77f8bfSYann Gautier 73*db77f8bfSYann Gautier assert(bank <= GPIO_BANK_K); 74*db77f8bfSYann Gautier 75*db77f8bfSYann Gautier return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 76*db77f8bfSYann Gautier } 77*db77f8bfSYann Gautier 78*db77f8bfSYann Gautier uintptr_t stm32_get_bkpr_boot_mode_addr(void) 79*db77f8bfSYann Gautier { 80*db77f8bfSYann Gautier return tamp_bkpr(BKPR_BOOT_MODE); 81*db77f8bfSYann Gautier } 82