1*35527fb4SYann Gautier /* 2*35527fb4SYann Gautier * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3*35527fb4SYann Gautier * 4*35527fb4SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*35527fb4SYann Gautier */ 6*35527fb4SYann Gautier 7*35527fb4SYann Gautier #ifndef PLATFORM_DEF_H 8*35527fb4SYann Gautier #define PLATFORM_DEF_H 9*35527fb4SYann Gautier 10*35527fb4SYann Gautier #include <arch.h> 11*35527fb4SYann Gautier #include <lib/utils_def.h> 12*35527fb4SYann Gautier #include <plat/common/common_def.h> 13*35527fb4SYann Gautier 14*35527fb4SYann Gautier #include "../stm32mp2_def.h" 15*35527fb4SYann Gautier 16*35527fb4SYann Gautier /******************************************************************************* 17*35527fb4SYann Gautier * Generic platform constants 18*35527fb4SYann Gautier ******************************************************************************/ 19*35527fb4SYann Gautier 20*35527fb4SYann Gautier /* Size of cacheable stacks */ 21*35527fb4SYann Gautier #define PLATFORM_STACK_SIZE 0xC00 22*35527fb4SYann Gautier 23*35527fb4SYann Gautier #define STM32MP_PRIMARY_CPU U(0x0) 24*35527fb4SYann Gautier #define STM32MP_SECONDARY_CPU U(0x1) 25*35527fb4SYann Gautier 26*35527fb4SYann Gautier #define MAX_IO_DEVICES U(4) 27*35527fb4SYann Gautier #define MAX_IO_HANDLES U(4) 28*35527fb4SYann Gautier #define MAX_IO_BLOCK_DEVICES U(1) 29*35527fb4SYann Gautier #define MAX_IO_MTD_DEVICES U(1) 30*35527fb4SYann Gautier 31*35527fb4SYann Gautier #define PLATFORM_CLUSTER_COUNT U(1) 32*35527fb4SYann Gautier #define PLATFORM_CORE_COUNT U(2) 33*35527fb4SYann Gautier #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 34*35527fb4SYann Gautier 35*35527fb4SYann Gautier #define PLAT_MAX_PWR_LVL U(5) 36*35527fb4SYann Gautier #define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5) 37*35527fb4SYann Gautier #define PLAT_NUM_PWR_DOMAINS U(7) 38*35527fb4SYann Gautier 39*35527fb4SYann Gautier /* Local power state for power domains in Run state. */ 40*35527fb4SYann Gautier #define STM32MP_LOCAL_STATE_RUN U(0) 41*35527fb4SYann Gautier /* Local power state for retention. */ 42*35527fb4SYann Gautier #define STM32MP_LOCAL_STATE_RET U(1) 43*35527fb4SYann Gautier #define STM32MP_LOCAL_STATE_LP U(2) 44*35527fb4SYann Gautier #define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP 45*35527fb4SYann Gautier /* Local power state for OFF/power-down. */ 46*35527fb4SYann Gautier #define STM32MP_LOCAL_STATE_OFF U(3) 47*35527fb4SYann Gautier #define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF 48*35527fb4SYann Gautier 49*35527fb4SYann Gautier /* Macros to parse the state information from State-ID (recommended encoding) */ 50*35527fb4SYann Gautier #define PLAT_LOCAL_PSTATE_WIDTH U(4) 51*35527fb4SYann Gautier #define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) 52*35527fb4SYann Gautier 53*35527fb4SYann Gautier /******************************************************************************* 54*35527fb4SYann Gautier * BL2 specific defines. 55*35527fb4SYann Gautier ******************************************************************************/ 56*35527fb4SYann Gautier /* 57*35527fb4SYann Gautier * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 58*35527fb4SYann Gautier * size plus a little space for growth. 59*35527fb4SYann Gautier */ 60*35527fb4SYann Gautier #define BL2_BASE STM32MP_BL2_BASE 61*35527fb4SYann Gautier #define BL2_LIMIT (STM32MP_BL2_BASE + \ 62*35527fb4SYann Gautier STM32MP_BL2_SIZE) 63*35527fb4SYann Gautier 64*35527fb4SYann Gautier /******************************************************************************* 65*35527fb4SYann Gautier * BL33 specific defines. 66*35527fb4SYann Gautier ******************************************************************************/ 67*35527fb4SYann Gautier #define BL33_BASE STM32MP_BL33_BASE 68*35527fb4SYann Gautier 69*35527fb4SYann Gautier /******************************************************************************* 70*35527fb4SYann Gautier * Platform specific page table and MMU setup constants 71*35527fb4SYann Gautier ******************************************************************************/ 72*35527fb4SYann Gautier #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) 73*35527fb4SYann Gautier #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) 74*35527fb4SYann Gautier 75*35527fb4SYann Gautier /******************************************************************************* 76*35527fb4SYann Gautier * Declarations and constants to access the mailboxes safely. Each mailbox is 77*35527fb4SYann Gautier * aligned on the biggest cache line size in the platform. This is known only 78*35527fb4SYann Gautier * to the platform as it might have a combination of integrated and external 79*35527fb4SYann Gautier * caches. Such alignment ensures that two maiboxes do not sit on the same cache 80*35527fb4SYann Gautier * line at any cache level. They could belong to different cpus/clusters & 81*35527fb4SYann Gautier * get written while being protected by different locks causing corruption of 82*35527fb4SYann Gautier * a valid mailbox address. 83*35527fb4SYann Gautier ******************************************************************************/ 84*35527fb4SYann Gautier #define CACHE_WRITEBACK_SHIFT 6 85*35527fb4SYann Gautier #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 86*35527fb4SYann Gautier 87*35527fb4SYann Gautier #endif /* PLATFORM_DEF_H */ 88