xref: /rk3399_ARM-atf/plat/st/stm32mp2/bl2_plat_setup.c (revision 52f530d3ab9d27db653670511b238d54e212cf0f) 
1 /*
2  * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <cdefs.h>
9 #include <errno.h>
10 #include <stdint.h>
11 
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/clk.h>
15 #include <drivers/mmc.h>
16 #include <drivers/st/regulator_fixed.h>
17 #include <drivers/st/stm32mp2_ddr_helpers.h>
18 #include <drivers/st/stm32mp_pmic2.h>
19 #include <drivers/st/stm32mp_risab_regs.h>
20 #include <lib/fconf/fconf.h>
21 #include <lib/fconf/fconf_dyn_cfg_getter.h>
22 #include <lib/mmio.h>
23 #include <lib/xlat_tables/xlat_tables_v2.h>
24 #include <plat/common/platform.h>
25 
26 #include <platform_def.h>
27 #include <stm32mp_common.h>
28 #include <stm32mp_dt.h>
29 
30 #define BOOT_CTX_ADDR	0x0e000020UL
31 
32 static void print_reset_reason(void)
33 {
34 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
35 
36 	if (rstsr == 0U) {
37 		WARN("Reset reason unknown\n");
38 		return;
39 	}
40 
41 	INFO("Reset reason (0x%x):\n", rstsr);
42 
43 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
44 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
45 			INFO("System exits from Standby for CA35\n");
46 			return;
47 		}
48 
49 		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
50 			INFO("D1 domain exits from DStandby\n");
51 			return;
52 		}
53 	}
54 
55 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
56 		INFO("  Power-on Reset (rst_por)\n");
57 		return;
58 	}
59 
60 	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
61 		INFO("  Brownout Reset (rst_bor)\n");
62 		return;
63 	}
64 
65 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
66 		INFO("  System reset (SYSRST) by M33\n");
67 		return;
68 	}
69 
70 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
71 		INFO("  System reset (SYSRST) by A35\n");
72 		return;
73 	}
74 
75 	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
76 		INFO("  Clock failure on HSE\n");
77 		return;
78 	}
79 
80 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
81 		INFO("  IWDG1 system reset (rst_iwdg1)\n");
82 		return;
83 	}
84 
85 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
86 		INFO("  IWDG2 system reset (rst_iwdg2)\n");
87 		return;
88 	}
89 
90 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
91 		INFO("  IWDG3 system reset (rst_iwdg3)\n");
92 		return;
93 	}
94 
95 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
96 		INFO("  IWDG4 system reset (rst_iwdg4)\n");
97 		return;
98 	}
99 
100 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
101 		INFO("  IWDG5 system reset (rst_iwdg5)\n");
102 		return;
103 	}
104 
105 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
106 		INFO("  A35 processor core 1 reset\n");
107 		return;
108 	}
109 
110 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
111 		INFO("  Pad Reset from NRST\n");
112 		return;
113 	}
114 
115 	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
116 		INFO("  Reset due to a failure of VDD_CORE\n");
117 		return;
118 	}
119 
120 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
121 		INFO("  A35 processor reset\n");
122 		return;
123 	}
124 
125 	ERROR("  Unidentified reset reason\n");
126 }
127 
128 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
129 				  u_register_t arg1 __unused,
130 				  u_register_t arg2 __unused,
131 				  u_register_t arg3 __unused)
132 {
133 	stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR);
134 }
135 
136 void bl2_platform_setup(void)
137 {
138 }
139 
140 static void reset_backup_domain(void)
141 {
142 	uintptr_t pwr_base = stm32mp_pwr_base();
143 	uintptr_t rcc_base = stm32mp_rcc_base();
144 
145 	/*
146 	 * Disable the backup domain write protection.
147 	 * The protection is enable at each reset by hardware
148 	 * and must be disabled by software.
149 	 */
150 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
151 
152 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
153 		;
154 	}
155 
156 	/* Reset backup domain on cold boot cases */
157 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
158 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
159 
160 		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) {
161 			;
162 		}
163 
164 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
165 	}
166 }
167 
168 void bl2_el3_plat_arch_setup(void)
169 {
170 	const char *board_model;
171 	boot_api_context_t *boot_context =
172 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
173 
174 	if (stm32_otp_probe() != 0U) {
175 		EARLY_ERROR("OTP probe failed\n");
176 		panic();
177 	}
178 
179 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
180 			BL_CODE_END - BL_CODE_BASE,
181 			MT_CODE | MT_SECURE);
182 
183 	configure_mmu();
184 
185 	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
186 		panic();
187 	}
188 
189 	reset_backup_domain();
190 
191 	/*
192 	 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
193 	 * and so before stm32mp2_clk_init().
194 	 */
195 	ddr_sub_system_clk_init();
196 
197 	if (stm32mp2_clk_init() < 0) {
198 		panic();
199 	}
200 
201 #if STM32MP_DDR_FIP_IO_STORAGE
202 	/*
203 	 * RISAB3 setup (dedicated for SRAM1)
204 	 *
205 	 * Allow secure read/writes data accesses to non-secure
206 	 * blocks or pages, all RISAB registers are writable.
207 	 * DDR firmwares are saved there before being loaded in DDRPHY memory.
208 	 */
209 	mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
210 #endif
211 
212 	stm32_save_boot_info(boot_context);
213 
214 	if (stm32mp_uart_console_setup() != 0) {
215 		goto skip_console_init;
216 	}
217 
218 	stm32mp_print_cpuinfo();
219 
220 	board_model = dt_get_board_model();
221 	if (board_model != NULL) {
222 		NOTICE("Model: %s\n", board_model);
223 	}
224 
225 	stm32mp_print_boardinfo();
226 
227 	print_reset_reason();
228 
229 skip_console_init:
230 	if (fixed_regulator_register() != 0) {
231 		panic();
232 	}
233 
234 	if (dt_pmic_status() > 0) {
235 		initialize_pmic();
236 	}
237 
238 	fconf_populate("TB_FW", STM32MP_DTB_BASE);
239 
240 	/*
241 	 * RISAB5 setup (dedicated for RETRAM)
242 	 *
243 	 * Allow secure read/writes data accesses to non-secure
244 	 * blocks or pages, all RISAB registers are writable.
245 	 * DDR retention registers are saved there and restored
246 	 * when exiting standby low power state.
247 	 */
248 	mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD);
249 
250 	stm32mp_io_setup();
251 }
252 
253 /*******************************************************************************
254  * This function can be used by the platforms to update/use image
255  * information for given `image_id`.
256  ******************************************************************************/
257 int bl2_plat_handle_post_image_load(unsigned int image_id)
258 {
259 	int err = 0;
260 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
261 	const struct dyn_cfg_dtb_info_t *config_info;
262 	unsigned int i;
263 	const unsigned int image_ids[] = {
264 		BL31_IMAGE_ID,
265 	};
266 
267 	assert(bl_mem_params != NULL);
268 
269 #if STM32MP_SDMMC || STM32MP_EMMC
270 	/*
271 	 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
272 	 * We take the worst case which is 2 MMC blocks.
273 	 */
274 	if ((image_id != FW_CONFIG_ID) &&
275 	    ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
276 		inv_dcache_range(bl_mem_params->image_info.image_base +
277 				 bl_mem_params->image_info.image_size,
278 				 2U * MMC_BLOCK_SIZE);
279 	}
280 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
281 
282 	switch (image_id) {
283 	case FW_CONFIG_ID:
284 		/* Set global DTB info for fixed fw_config information */
285 		set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
286 				FW_CONFIG_ID);
287 		fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
288 
289 		/* Iterate through all the fw config IDs */
290 		for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
291 			bl_mem_params = get_bl_mem_params_node(image_ids[i]);
292 			assert(bl_mem_params != NULL);
293 
294 			config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
295 			if (config_info == NULL) {
296 				continue;
297 			}
298 
299 			bl_mem_params->image_info.image_base = config_info->config_addr;
300 			bl_mem_params->image_info.image_max_size = config_info->config_max_size;
301 
302 			bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
303 
304 			switch (image_ids[i]) {
305 			case BL31_IMAGE_ID:
306 				bl_mem_params->ep_info.pc = config_info->config_addr;
307 				break;
308 			default:
309 				return -EINVAL;
310 			}
311 		}
312 
313 		/*
314 		 * After this step, the BL2 device tree area will be overwritten
315 		 * with BL31 binary, no other data should be read from BL2 DT.
316 		 */
317 
318 		break;
319 
320 	default:
321 		/* Do nothing in default case */
322 		break;
323 	}
324 
325 	return err;
326 }
327