1 /* 2 * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <stdint.h> 8 9 #include <platform_def.h> 10 11 #include <drivers/clk.h> 12 #include <drivers/scmi-msg.h> 13 #include <drivers/scmi.h> 14 #include <drivers/st/stm32mp1_clk.h> 15 #include <drivers/st/stm32mp_reset.h> 16 #include <dt-bindings/clock/stm32mp1-clks.h> 17 #include <dt-bindings/reset/stm32mp1-resets.h> 18 19 #define TIMEOUT_US_1MS 1000U 20 21 #define SCMI_CLOCK_NAME_SIZE 16U 22 #define SCMI_RSTD_NAME_SIZE 16U 23 24 /* 25 * struct stm32_scmi_clk - Data for the exposed clock 26 * @clock_id: Clock identifier in RCC clock driver 27 * @name: Clock string ID exposed to agent 28 * @enabled: State of the SCMI clock 29 */ 30 struct stm32_scmi_clk { 31 unsigned long clock_id; 32 const char *name; 33 bool enabled; 34 }; 35 36 /* 37 * struct stm32_scmi_rstd - Data for the exposed reset controller 38 * @reset_id: Reset identifier in RCC reset driver 39 * @name: Reset string ID exposed to agent 40 */ 41 struct stm32_scmi_rstd { 42 unsigned long reset_id; 43 const char *name; 44 }; 45 46 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 47 #define SMT_BUFFER_BASE STM32MP_SCMI_NS_SHM_BASE 48 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 49 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 50 51 CASSERT((STM32MP_SCMI_NS_SHM_BASE + STM32MP_SCMI_NS_SHM_SIZE) >= 52 (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE), 53 assert_scmi_non_secure_shm_fits_scmi_overall_buffer_size); 54 55 static struct scmi_msg_channel scmi_channel[] = { 56 [0] = { 57 .shm_addr = SMT_BUFFER0_BASE, 58 .shm_size = SMT_BUF_SLOT_SIZE, 59 }, 60 [1] = { 61 .shm_addr = SMT_BUFFER1_BASE, 62 .shm_size = SMT_BUF_SLOT_SIZE, 63 }, 64 }; 65 66 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 67 { 68 assert(agent_id < ARRAY_SIZE(scmi_channel)); 69 70 return &scmi_channel[agent_id]; 71 } 72 73 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 74 [_scmi_id] = { \ 75 .clock_id = _id, \ 76 .name = _name, \ 77 .enabled = _init_enabled, \ 78 } 79 80 static struct stm32_scmi_clk stm32_scmi0_clock[] = { 81 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 82 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 83 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 84 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 85 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 86 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 87 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 88 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 89 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 90 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 91 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 92 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 93 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 94 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 95 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 96 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 97 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 98 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 99 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 100 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 101 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 102 }; 103 104 static struct stm32_scmi_clk stm32_scmi1_clock[] = { 105 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 106 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 107 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 108 }; 109 110 #define RESET_CELL(_scmi_id, _id, _name) \ 111 [_scmi_id] = { \ 112 .reset_id = _id, \ 113 .name = _name, \ 114 } 115 116 static struct stm32_scmi_rstd stm32_scmi0_reset_domain[] = { 117 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 118 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 119 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 120 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 121 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 122 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 123 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 124 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 125 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 126 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 127 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 128 }; 129 130 struct scmi_agent_resources { 131 struct stm32_scmi_clk *clock; 132 size_t clock_count; 133 struct stm32_scmi_rstd *rstd; 134 size_t rstd_count; 135 }; 136 137 static const struct scmi_agent_resources agent_resources[] = { 138 [0] = { 139 .clock = stm32_scmi0_clock, 140 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 141 .rstd = stm32_scmi0_reset_domain, 142 .rstd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 143 }, 144 [1] = { 145 .clock = stm32_scmi1_clock, 146 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 147 }, 148 }; 149 150 static const struct scmi_agent_resources *find_resource(unsigned int agent_id) 151 { 152 assert(agent_id < ARRAY_SIZE(agent_resources)); 153 154 return &agent_resources[agent_id]; 155 } 156 157 #if ENABLE_ASSERTIONS 158 static size_t plat_scmi_protocol_count_paranoid(void) 159 { 160 unsigned int n = 0U; 161 unsigned int count = 0U; 162 163 for (n = 0U; n < ARRAY_SIZE(agent_resources); n++) { 164 if (agent_resources[n].clock_count) { 165 count++; 166 break; 167 } 168 } 169 170 for (n = 0U; n < ARRAY_SIZE(agent_resources); n++) { 171 if (agent_resources[n].rstd_count) { 172 count++; 173 break; 174 } 175 } 176 177 return count; 178 } 179 #endif 180 181 static const char vendor[] = "ST"; 182 static const char sub_vendor[] = ""; 183 184 const char *plat_scmi_vendor_name(void) 185 { 186 return vendor; 187 } 188 189 const char *plat_scmi_sub_vendor_name(void) 190 { 191 return sub_vendor; 192 } 193 194 /* Currently supporting Clocks and Reset Domains */ 195 static const uint8_t plat_protocol_list[] = { 196 SCMI_PROTOCOL_ID_CLOCK, 197 SCMI_PROTOCOL_ID_RESET_DOMAIN, 198 0U /* Null termination */ 199 }; 200 201 size_t plat_scmi_protocol_count(void) 202 { 203 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; 204 205 assert(count == plat_scmi_protocol_count_paranoid()); 206 207 return count; 208 } 209 210 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 211 { 212 assert(plat_scmi_protocol_count_paranoid() == 213 (ARRAY_SIZE(plat_protocol_list) - 1U)); 214 215 return plat_protocol_list; 216 } 217 218 /* 219 * Platform SCMI clocks 220 */ 221 static struct stm32_scmi_clk *find_clock(unsigned int agent_id, 222 unsigned int scmi_id) 223 { 224 const struct scmi_agent_resources *resource = find_resource(agent_id); 225 size_t n = 0U; 226 227 if (resource != NULL) { 228 for (n = 0U; n < resource->clock_count; n++) { 229 if (n == scmi_id) { 230 return &resource->clock[n]; 231 } 232 } 233 } 234 235 return NULL; 236 } 237 238 size_t plat_scmi_clock_count(unsigned int agent_id) 239 { 240 const struct scmi_agent_resources *resource = find_resource(agent_id); 241 242 if (resource == NULL) { 243 return 0U; 244 } 245 246 return resource->clock_count; 247 } 248 249 const char *plat_scmi_clock_get_name(unsigned int agent_id, 250 unsigned int scmi_id) 251 { 252 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 253 254 if ((clock == NULL) || 255 !stm32mp_nsec_can_access_clock(clock->clock_id)) { 256 return NULL; 257 } 258 259 return clock->name; 260 } 261 262 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 263 unsigned long *array, size_t *nb_elts, 264 uint32_t start_idx) 265 { 266 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 267 268 if (clock == NULL) { 269 return SCMI_NOT_FOUND; 270 } 271 272 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) { 273 return SCMI_DENIED; 274 } 275 276 if (start_idx > 0) { 277 return SCMI_OUT_OF_RANGE; 278 } 279 280 if (array == NULL) { 281 *nb_elts = 1U; 282 } else if (*nb_elts == 1U) { 283 *array = clk_get_rate(clock->clock_id); 284 } else { 285 return SCMI_GENERIC_ERROR; 286 } 287 288 return SCMI_SUCCESS; 289 } 290 291 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, 292 unsigned int scmi_id) 293 { 294 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 295 296 if ((clock == NULL) || 297 !stm32mp_nsec_can_access_clock(clock->clock_id)) { 298 return 0U; 299 } 300 301 return clk_get_rate(clock->clock_id); 302 } 303 304 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 305 { 306 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 307 308 if ((clock == NULL) || 309 !stm32mp_nsec_can_access_clock(clock->clock_id)) { 310 return 0U; 311 } 312 313 return (int32_t)clock->enabled; 314 } 315 316 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 317 bool enable_not_disable) 318 { 319 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 320 321 if (clock == NULL) { 322 return SCMI_NOT_FOUND; 323 } 324 325 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) { 326 return SCMI_DENIED; 327 } 328 329 if (enable_not_disable) { 330 if (!clock->enabled) { 331 VERBOSE("SCMI clock %u enable\n", scmi_id); 332 clk_enable(clock->clock_id); 333 clock->enabled = true; 334 } 335 } else { 336 if (clock->enabled) { 337 VERBOSE("SCMI clock %u disable\n", scmi_id); 338 clk_disable(clock->clock_id); 339 clock->enabled = false; 340 } 341 } 342 343 return SCMI_SUCCESS; 344 } 345 346 /* 347 * Platform SCMI reset domains 348 */ 349 static struct stm32_scmi_rstd *find_rstd(unsigned int agent_id, 350 unsigned int scmi_id) 351 { 352 const struct scmi_agent_resources *resource = find_resource(agent_id); 353 size_t n; 354 355 if (resource != NULL) { 356 for (n = 0U; n < resource->rstd_count; n++) { 357 if (n == scmi_id) { 358 return &resource->rstd[n]; 359 } 360 } 361 } 362 363 return NULL; 364 } 365 366 const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id) 367 { 368 const struct stm32_scmi_rstd *rstd = find_rstd(agent_id, scmi_id); 369 370 if (rstd == NULL) { 371 return NULL; 372 } 373 374 return rstd->name; 375 } 376 377 size_t plat_scmi_rstd_count(unsigned int agent_id) 378 { 379 const struct scmi_agent_resources *resource = find_resource(agent_id); 380 381 if (resource == NULL) { 382 return 0U; 383 } 384 385 return resource->rstd_count; 386 } 387 388 int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, 389 uint32_t state) 390 { 391 const struct stm32_scmi_rstd *rstd = find_rstd(agent_id, scmi_id); 392 393 if (rstd == NULL) { 394 return SCMI_NOT_FOUND; 395 } 396 397 if (!stm32mp_nsec_can_access_reset(rstd->reset_id)) { 398 return SCMI_DENIED; 399 } 400 401 /* Supports only reset with context loss */ 402 if (state != 0U) { 403 return SCMI_NOT_SUPPORTED; 404 } 405 406 VERBOSE("SCMI reset %lu cycle\n", rstd->reset_id); 407 408 if (stm32mp_reset_assert(rstd->reset_id, TIMEOUT_US_1MS)) { 409 return SCMI_HARDWARE_ERROR; 410 } 411 412 if (stm32mp_reset_deassert(rstd->reset_id, TIMEOUT_US_1MS)) { 413 return SCMI_HARDWARE_ERROR; 414 } 415 416 return SCMI_SUCCESS; 417 } 418 419 int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, 420 bool assert_not_deassert) 421 { 422 const struct stm32_scmi_rstd *rstd = find_rstd(agent_id, scmi_id); 423 424 if (rstd == NULL) { 425 return SCMI_NOT_FOUND; 426 } 427 428 if (!stm32mp_nsec_can_access_reset(rstd->reset_id)) { 429 return SCMI_DENIED; 430 } 431 432 if (assert_not_deassert) { 433 VERBOSE("SCMI reset %lu set\n", rstd->reset_id); 434 stm32mp_reset_set(rstd->reset_id); 435 } else { 436 VERBOSE("SCMI reset %lu release\n", rstd->reset_id); 437 stm32mp_reset_release(rstd->reset_id); 438 } 439 440 return SCMI_SUCCESS; 441 } 442 443 /* 444 * Initialize platform SCMI resources 445 */ 446 void stm32mp1_init_scmi_server(void) 447 { 448 size_t i; 449 450 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) { 451 scmi_smt_init_agent_channel(&scmi_channel[i]); 452 } 453 454 for (i = 0U; i < ARRAY_SIZE(agent_resources); i++) { 455 const struct scmi_agent_resources *res = &agent_resources[i]; 456 size_t j; 457 458 for (j = 0U; j < res->clock_count; j++) { 459 struct stm32_scmi_clk *clk = &res->clock[j]; 460 461 if ((clk->name == NULL) || 462 (strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE)) { 463 ERROR("Invalid SCMI clock name\n"); 464 panic(); 465 } 466 467 /* Sync SCMI clocks with their targeted initial state */ 468 if (clk->enabled && 469 stm32mp_nsec_can_access_clock(clk->clock_id)) { 470 clk_enable(clk->clock_id); 471 } 472 } 473 474 for (j = 0U; j < res->rstd_count; j++) { 475 struct stm32_scmi_rstd *rstd = &res->rstd[j]; 476 477 if ((rstd->name == NULL) || 478 (strlen(rstd->name) >= SCMI_RSTD_NAME_SIZE)) { 479 ERROR("Invalid SCMI reset domain name\n"); 480 panic(); 481 } 482 } 483 } 484 } 485