1 /* 2 * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_FIP_DEF_H 8 #define STM32MP1_FIP_DEF_H 9 10 #if STM32MP15_OPTEE_RSV_SHM 11 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 12 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 13 #else 14 #define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ 15 #define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ 16 #endif 17 18 #if STM32MP13 19 #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ 20 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ 21 #define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ 22 #endif /* STM32MP13 */ 23 #if STM32MP15 24 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ 25 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ 26 #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ 27 #endif /* STM32MP15 */ 28 #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ 29 #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 30 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ 31 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ 32 33 #if STM32MP13 34 #define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ 35 STM32MP_BL2_DTB_SIZE) 36 #endif /* STM32MP13 */ 37 #if STM32MP15 38 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 39 STM32MP_SEC_SYSRAM_SIZE - \ 40 STM32MP_BL2_SIZE) 41 #endif /* STM32MP15 */ 42 43 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 44 45 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 46 STM32MP_BL2_RO_SIZE) 47 48 #if STM32MP13 49 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 50 STM32MP_SYSRAM_SIZE - \ 51 STM32MP_BL2_RW_BASE) 52 53 #define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE 54 #endif /* STM32MP13 */ 55 #if STM32MP15 56 #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ 57 STM32MP_SEC_SYSRAM_SIZE - \ 58 STM32MP_BL2_RW_BASE) 59 60 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 61 STM32MP_BL2_DTB_SIZE) 62 #endif /* STM32MP15 */ 63 64 #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE 65 66 #define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \ 67 STM32MP_BL32_DTB_SIZE) 68 69 70 #if defined(IMAGE_BL2) 71 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 72 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 73 #endif 74 #if defined(IMAGE_BL32) 75 #define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE 76 #define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE 77 #endif 78 79 #ifdef AARCH32_SP_OPTEE 80 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 81 82 #define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \ 83 STM32MP_OPTEE_BASE) 84 #endif 85 86 #if STM32MP13 87 #define STM32MP_FW_CONFIG_BASE SRAM3_BASE 88 #endif /* STM32MP13 */ 89 #if STM32MP15 90 #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ 91 STM32MP_SYSRAM_SIZE - \ 92 PAGE_SIZE) 93 #endif /* STM32MP15 */ 94 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 95 STM32MP_BL33_MAX_SIZE) 96 97 /* 98 * MAX_MMAP_REGIONS is usually: 99 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 100 */ 101 #if defined(IMAGE_BL32) 102 #define MAX_MMAP_REGIONS 10 103 #endif 104 105 /******************************************************************************* 106 * STM32MP1 RAW partition offset for devices without GPT 107 ******************************************************************************/ 108 #define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000) 109 #ifndef STM32MP_NOR_FIP_OFFSET 110 #define STM32MP_NOR_FIP_OFFSET U(0x00080000) 111 #endif 112 #ifndef STM32MP_NAND_FIP_OFFSET 113 #define STM32MP_NAND_FIP_OFFSET U(0x00200000) 114 #endif 115 116 #endif /* STM32MP1_FIP_DEF_H */ 117