1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #include <stm32mp1_shared_resources.h> 28 #endif 29 30 #if !STM32MP_USE_STM32IMAGE 31 #include "stm32mp1_fip_def.h" 32 #else /* STM32MP_USE_STM32IMAGE */ 33 #include "stm32mp1_stm32image_def.h" 34 #endif /* STM32MP_USE_STM32IMAGE */ 35 36 /******************************************************************************* 37 * CHIP ID 38 ******************************************************************************/ 39 #define STM32MP1_CHIP_ID U(0x500) 40 41 #define STM32MP157C_PART_NB U(0x05000000) 42 #define STM32MP157A_PART_NB U(0x05000001) 43 #define STM32MP153C_PART_NB U(0x05000024) 44 #define STM32MP153A_PART_NB U(0x05000025) 45 #define STM32MP151C_PART_NB U(0x0500002E) 46 #define STM32MP151A_PART_NB U(0x0500002F) 47 #define STM32MP157F_PART_NB U(0x05000080) 48 #define STM32MP157D_PART_NB U(0x05000081) 49 #define STM32MP153F_PART_NB U(0x050000A4) 50 #define STM32MP153D_PART_NB U(0x050000A5) 51 #define STM32MP151F_PART_NB U(0x050000AE) 52 #define STM32MP151D_PART_NB U(0x050000AF) 53 54 #define STM32MP1_REV_B U(0x2000) 55 #if STM32MP13 56 #define STM32MP1_REV_Z U(0x1001) 57 #endif 58 #if STM32MP15 59 #define STM32MP1_REV_Z U(0x2001) 60 #endif 61 62 /******************************************************************************* 63 * PACKAGE ID 64 ******************************************************************************/ 65 #define PKG_AA_LFBGA448 U(4) 66 #define PKG_AB_LFBGA354 U(3) 67 #define PKG_AC_TFBGA361 U(2) 68 #define PKG_AD_TFBGA257 U(1) 69 70 /******************************************************************************* 71 * STM32MP1 memory map related constants 72 ******************************************************************************/ 73 #define STM32MP_ROM_BASE U(0x00000000) 74 #define STM32MP_ROM_SIZE U(0x00020000) 75 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 76 77 #if STM32MP13 78 #define STM32MP_SYSRAM_BASE U(0x2FFE0000) 79 #define STM32MP_SYSRAM_SIZE U(0x00020000) 80 #define SRAM1_BASE U(0x30000000) 81 #define SRAM1_SIZE U(0x00004000) 82 #define SRAM2_BASE U(0x30004000) 83 #define SRAM2_SIZE U(0x00002000) 84 #define SRAM3_BASE U(0x30006000) 85 #define SRAM3_SIZE U(0x00002000) 86 #endif /* STM32MP13 */ 87 #if STM32MP15 88 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 89 #define STM32MP_SYSRAM_SIZE U(0x00040000) 90 #endif /* STM32MP15 */ 91 92 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 93 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 94 STM32MP_SYSRAM_SIZE - \ 95 STM32MP_NS_SYSRAM_SIZE) 96 97 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 98 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 99 100 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 101 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 102 STM32MP_NS_SYSRAM_SIZE) 103 104 /* DDR configuration */ 105 #define STM32MP_DDR_BASE U(0xC0000000) 106 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 107 108 /* DDR power initializations */ 109 #ifndef __ASSEMBLER__ 110 enum ddr_type { 111 STM32MP_DDR3, 112 STM32MP_LPDDR2, 113 STM32MP_LPDDR3 114 }; 115 #endif 116 117 /* Section used inside TF binaries */ 118 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 119 /* 256 Octets reserved for header */ 120 #define STM32MP_HEADER_SIZE U(0x00000100) 121 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 122 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 123 124 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 125 STM32MP_PARAM_LOAD_SIZE + \ 126 STM32MP_HEADER_SIZE) 127 128 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 129 (STM32MP_PARAM_LOAD_SIZE + \ 130 STM32MP_HEADER_SIZE)) 131 132 /* BL2 and BL32/sp_min require finer granularity tables */ 133 #if defined(IMAGE_BL2) 134 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 135 #endif 136 137 #if defined(IMAGE_BL32) 138 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 139 #endif 140 141 /* 142 * MAX_MMAP_REGIONS is usually: 143 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 144 */ 145 #if defined(IMAGE_BL2) 146 #if STM32MP_USB_PROGRAMMER 147 #define MAX_MMAP_REGIONS 8 148 #else 149 #define MAX_MMAP_REGIONS 7 150 #endif 151 #endif 152 153 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 154 #define STM32MP_BL33_MAX_SIZE U(0x400000) 155 156 /* Define maximum page size for NAND devices */ 157 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 158 159 /******************************************************************************* 160 * STM32MP1 device/io map related constants (used for MMU) 161 ******************************************************************************/ 162 #define STM32MP1_DEVICE1_BASE U(0x40000000) 163 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 164 165 #define STM32MP1_DEVICE2_BASE U(0x80000000) 166 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 167 168 /******************************************************************************* 169 * STM32MP1 RCC 170 ******************************************************************************/ 171 #define RCC_BASE U(0x50000000) 172 173 /******************************************************************************* 174 * STM32MP1 PWR 175 ******************************************************************************/ 176 #define PWR_BASE U(0x50001000) 177 178 /******************************************************************************* 179 * STM32MP1 GPIO 180 ******************************************************************************/ 181 #define GPIOA_BASE U(0x50002000) 182 #define GPIOB_BASE U(0x50003000) 183 #define GPIOC_BASE U(0x50004000) 184 #define GPIOD_BASE U(0x50005000) 185 #define GPIOE_BASE U(0x50006000) 186 #define GPIOF_BASE U(0x50007000) 187 #define GPIOG_BASE U(0x50008000) 188 #define GPIOH_BASE U(0x50009000) 189 #define GPIOI_BASE U(0x5000A000) 190 #if STM32MP15 191 #define GPIOJ_BASE U(0x5000B000) 192 #define GPIOK_BASE U(0x5000C000) 193 #define GPIOZ_BASE U(0x54004000) 194 #endif 195 #define GPIO_BANK_OFFSET U(0x1000) 196 197 /* Bank IDs used in GPIO driver API */ 198 #define GPIO_BANK_A U(0) 199 #define GPIO_BANK_B U(1) 200 #define GPIO_BANK_C U(2) 201 #define GPIO_BANK_D U(3) 202 #define GPIO_BANK_E U(4) 203 #define GPIO_BANK_F U(5) 204 #define GPIO_BANK_G U(6) 205 #define GPIO_BANK_H U(7) 206 #define GPIO_BANK_I U(8) 207 #if STM32MP15 208 #define GPIO_BANK_J U(9) 209 #define GPIO_BANK_K U(10) 210 #define GPIO_BANK_Z U(25) 211 212 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 213 #endif 214 215 /******************************************************************************* 216 * STM32MP1 UART 217 ******************************************************************************/ 218 #define USART1_BASE U(0x5C000000) 219 #define USART2_BASE U(0x4000E000) 220 #define USART3_BASE U(0x4000F000) 221 #define UART4_BASE U(0x40010000) 222 #define UART5_BASE U(0x40011000) 223 #define USART6_BASE U(0x44003000) 224 #define UART7_BASE U(0x40018000) 225 #define UART8_BASE U(0x40019000) 226 227 /* For UART crash console */ 228 #define STM32MP_DEBUG_USART_BASE UART4_BASE 229 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 230 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 231 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 232 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 233 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 234 #define DEBUG_UART_TX_GPIO_PORT 11 235 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 236 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 237 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 238 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 239 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 240 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 241 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 242 243 /******************************************************************************* 244 * STM32MP1 ETZPC 245 ******************************************************************************/ 246 #define STM32MP1_ETZPC_BASE U(0x5C007000) 247 248 /* ETZPC TZMA IDs */ 249 #define STM32MP1_ETZPC_TZMA_ROM U(0) 250 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 251 252 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 253 254 /* ETZPC DECPROT IDs */ 255 #define STM32MP1_ETZPC_STGENC_ID 0 256 #define STM32MP1_ETZPC_BKPSRAM_ID 1 257 #define STM32MP1_ETZPC_IWDG1_ID 2 258 #define STM32MP1_ETZPC_USART1_ID 3 259 #define STM32MP1_ETZPC_SPI6_ID 4 260 #define STM32MP1_ETZPC_I2C4_ID 5 261 #define STM32MP1_ETZPC_RNG1_ID 7 262 #define STM32MP1_ETZPC_HASH1_ID 8 263 #define STM32MP1_ETZPC_CRYP1_ID 9 264 #define STM32MP1_ETZPC_DDRCTRL_ID 10 265 #define STM32MP1_ETZPC_DDRPHYC_ID 11 266 #define STM32MP1_ETZPC_I2C6_ID 12 267 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 268 269 #define STM32MP1_ETZPC_TIM2_ID 16 270 #define STM32MP1_ETZPC_TIM3_ID 17 271 #define STM32MP1_ETZPC_TIM4_ID 18 272 #define STM32MP1_ETZPC_TIM5_ID 19 273 #define STM32MP1_ETZPC_TIM6_ID 20 274 #define STM32MP1_ETZPC_TIM7_ID 21 275 #define STM32MP1_ETZPC_TIM12_ID 22 276 #define STM32MP1_ETZPC_TIM13_ID 23 277 #define STM32MP1_ETZPC_TIM14_ID 24 278 #define STM32MP1_ETZPC_LPTIM1_ID 25 279 #define STM32MP1_ETZPC_WWDG1_ID 26 280 #define STM32MP1_ETZPC_SPI2_ID 27 281 #define STM32MP1_ETZPC_SPI3_ID 28 282 #define STM32MP1_ETZPC_SPDIFRX_ID 29 283 #define STM32MP1_ETZPC_USART2_ID 30 284 #define STM32MP1_ETZPC_USART3_ID 31 285 #define STM32MP1_ETZPC_UART4_ID 32 286 #define STM32MP1_ETZPC_UART5_ID 33 287 #define STM32MP1_ETZPC_I2C1_ID 34 288 #define STM32MP1_ETZPC_I2C2_ID 35 289 #define STM32MP1_ETZPC_I2C3_ID 36 290 #define STM32MP1_ETZPC_I2C5_ID 37 291 #define STM32MP1_ETZPC_CEC_ID 38 292 #define STM32MP1_ETZPC_DAC_ID 39 293 #define STM32MP1_ETZPC_UART7_ID 40 294 #define STM32MP1_ETZPC_UART8_ID 41 295 #define STM32MP1_ETZPC_MDIOS_ID 44 296 #define STM32MP1_ETZPC_TIM1_ID 48 297 #define STM32MP1_ETZPC_TIM8_ID 49 298 #define STM32MP1_ETZPC_USART6_ID 51 299 #define STM32MP1_ETZPC_SPI1_ID 52 300 #define STM32MP1_ETZPC_SPI4_ID 53 301 #define STM32MP1_ETZPC_TIM15_ID 54 302 #define STM32MP1_ETZPC_TIM16_ID 55 303 #define STM32MP1_ETZPC_TIM17_ID 56 304 #define STM32MP1_ETZPC_SPI5_ID 57 305 #define STM32MP1_ETZPC_SAI1_ID 58 306 #define STM32MP1_ETZPC_SAI2_ID 59 307 #define STM32MP1_ETZPC_SAI3_ID 60 308 #define STM32MP1_ETZPC_DFSDM_ID 61 309 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 310 #define STM32MP1_ETZPC_LPTIM2_ID 64 311 #define STM32MP1_ETZPC_LPTIM3_ID 65 312 #define STM32MP1_ETZPC_LPTIM4_ID 66 313 #define STM32MP1_ETZPC_LPTIM5_ID 67 314 #define STM32MP1_ETZPC_SAI4_ID 68 315 #define STM32MP1_ETZPC_VREFBUF_ID 69 316 #define STM32MP1_ETZPC_DCMI_ID 70 317 #define STM32MP1_ETZPC_CRC2_ID 71 318 #define STM32MP1_ETZPC_ADC_ID 72 319 #define STM32MP1_ETZPC_HASH2_ID 73 320 #define STM32MP1_ETZPC_RNG2_ID 74 321 #define STM32MP1_ETZPC_CRYP2_ID 75 322 #define STM32MP1_ETZPC_SRAM1_ID 80 323 #define STM32MP1_ETZPC_SRAM2_ID 81 324 #define STM32MP1_ETZPC_SRAM3_ID 82 325 #define STM32MP1_ETZPC_SRAM4_ID 83 326 #define STM32MP1_ETZPC_RETRAM_ID 84 327 #define STM32MP1_ETZPC_OTG_ID 85 328 #define STM32MP1_ETZPC_SDMMC3_ID 86 329 #define STM32MP1_ETZPC_DLYBSD3_ID 87 330 #define STM32MP1_ETZPC_DMA1_ID 88 331 #define STM32MP1_ETZPC_DMA2_ID 89 332 #define STM32MP1_ETZPC_DMAMUX_ID 90 333 #define STM32MP1_ETZPC_FMC_ID 91 334 #define STM32MP1_ETZPC_QSPI_ID 92 335 #define STM32MP1_ETZPC_DLYBQ_ID 93 336 #define STM32MP1_ETZPC_ETH_ID 94 337 #define STM32MP1_ETZPC_RSV_ID 95 338 339 #define STM32MP_ETZPC_MAX_ID 96 340 341 /******************************************************************************* 342 * STM32MP1 TZC (TZ400) 343 ******************************************************************************/ 344 #define STM32MP1_TZC_BASE U(0x5C006000) 345 346 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 347 TZC_400_REGION_ATTR_FILTER_BIT(1)) 348 349 /******************************************************************************* 350 * STM32MP1 SDMMC 351 ******************************************************************************/ 352 #define STM32MP_SDMMC1_BASE U(0x58005000) 353 #define STM32MP_SDMMC2_BASE U(0x58007000) 354 #define STM32MP_SDMMC3_BASE U(0x48004000) 355 356 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 357 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 358 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 359 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 360 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 361 362 /******************************************************************************* 363 * STM32MP1 BSEC / OTP 364 ******************************************************************************/ 365 #define STM32MP1_OTP_MAX_ID 0x5FU 366 #define STM32MP1_UPPER_OTP_START 0x20U 367 368 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 369 370 /* OTP labels */ 371 #define CFG0_OTP "cfg0_otp" 372 #define PART_NUMBER_OTP "part_number_otp" 373 #define PACKAGE_OTP "package_otp" 374 #define HW2_OTP "hw2_otp" 375 #define NAND_OTP "nand_otp" 376 #define MONOTONIC_OTP "monotonic_otp" 377 #define UID_OTP "uid_otp" 378 #define BOARD_ID_OTP "board_id" 379 380 /* OTP mask */ 381 /* CFG0 */ 382 #define CFG0_CLOSED_DEVICE BIT(6) 383 384 /* PART NUMBER */ 385 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 386 #define PART_NUMBER_OTP_PART_SHIFT 0 387 388 /* PACKAGE */ 389 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 390 #define PACKAGE_OTP_PKG_SHIFT 27 391 392 /* IWDG OTP */ 393 #define HW2_OTP_IWDG_HW_POS U(3) 394 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 395 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 396 397 /* HW2 OTP */ 398 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 399 400 /* NAND OTP */ 401 /* NAND parameter storage flag */ 402 #define NAND_PARAM_STORED_IN_OTP BIT(31) 403 404 /* NAND page size in bytes */ 405 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 406 #define NAND_PAGE_SIZE_SHIFT 29 407 #define NAND_PAGE_SIZE_2K U(0) 408 #define NAND_PAGE_SIZE_4K U(1) 409 #define NAND_PAGE_SIZE_8K U(2) 410 411 /* NAND block size in pages */ 412 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 413 #define NAND_BLOCK_SIZE_SHIFT 27 414 #define NAND_BLOCK_SIZE_64_PAGES U(0) 415 #define NAND_BLOCK_SIZE_128_PAGES U(1) 416 #define NAND_BLOCK_SIZE_256_PAGES U(2) 417 418 /* NAND number of block (in unit of 256 blocs) */ 419 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 420 #define NAND_BLOCK_NB_SHIFT 19 421 #define NAND_BLOCK_NB_UNIT U(256) 422 423 /* NAND bus width in bits */ 424 #define NAND_WIDTH_MASK BIT(18) 425 #define NAND_WIDTH_SHIFT 18 426 427 /* NAND number of ECC bits per 512 bytes */ 428 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 429 #define NAND_ECC_BIT_NB_SHIFT 15 430 #define NAND_ECC_BIT_NB_UNSET U(0) 431 #define NAND_ECC_BIT_NB_1_BITS U(1) 432 #define NAND_ECC_BIT_NB_4_BITS U(2) 433 #define NAND_ECC_BIT_NB_8_BITS U(3) 434 #define NAND_ECC_ON_DIE U(4) 435 436 /* NAND number of planes */ 437 #define NAND_PLANE_BIT_NB_MASK BIT(14) 438 439 /* MONOTONIC OTP */ 440 #define MAX_MONOTONIC_VALUE 32 441 442 /* UID OTP */ 443 #define UID_WORD_NB U(3) 444 445 /******************************************************************************* 446 * STM32MP1 TAMP 447 ******************************************************************************/ 448 #define TAMP_BASE U(0x5C00A000) 449 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 450 451 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 452 static inline uintptr_t tamp_bkpr(uint32_t idx) 453 { 454 return TAMP_BKP_REGISTER_BASE + (idx << 2); 455 } 456 #endif 457 458 /******************************************************************************* 459 * STM32MP1 USB 460 ******************************************************************************/ 461 #define USB_OTG_BASE U(0x49000000) 462 463 /******************************************************************************* 464 * STM32MP1 DDRCTRL 465 ******************************************************************************/ 466 #define DDRCTRL_BASE U(0x5A003000) 467 468 /******************************************************************************* 469 * STM32MP1 DDRPHYC 470 ******************************************************************************/ 471 #define DDRPHYC_BASE U(0x5A004000) 472 473 /******************************************************************************* 474 * STM32MP1 IWDG 475 ******************************************************************************/ 476 #define IWDG_MAX_INSTANCE U(2) 477 #define IWDG1_INST U(0) 478 #define IWDG2_INST U(1) 479 480 #define IWDG1_BASE U(0x5C003000) 481 #define IWDG2_BASE U(0x5A002000) 482 483 /******************************************************************************* 484 * Miscellaneous STM32MP1 peripherals base address 485 ******************************************************************************/ 486 #define BSEC_BASE U(0x5C005000) 487 #define CRYP1_BASE U(0x54001000) 488 #define DBGMCU_BASE U(0x50081000) 489 #define HASH1_BASE U(0x54002000) 490 #define I2C4_BASE U(0x5C002000) 491 #define I2C6_BASE U(0x5c009000) 492 #define RNG1_BASE U(0x54003000) 493 #define RTC_BASE U(0x5c004000) 494 #define SPI6_BASE U(0x5c001000) 495 #define STGEN_BASE U(0x5c008000) 496 #define SYSCFG_BASE U(0x50020000) 497 498 /******************************************************************************* 499 * REGULATORS 500 ******************************************************************************/ 501 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 502 #define PLAT_NB_RDEVS U(19) 503 /* 1 FIXED */ 504 #define PLAT_NB_FIXED_REGS U(1) 505 506 /******************************************************************************* 507 * Device Tree defines 508 ******************************************************************************/ 509 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 510 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 511 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 512 #define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout" 513 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 514 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 515 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 516 517 #endif /* STM32MP1_DEF_H */ 518