1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLY__ 18 #include <drivers/st/stm32mp1_clk.h> 19 20 #include <boot_api.h> 21 #include <stm32mp_common.h> 22 #include <stm32mp_dt.h> 23 #include <stm32mp1_private.h> 24 #endif 25 26 /******************************************************************************* 27 * STM32MP1 memory map related constants 28 ******************************************************************************/ 29 30 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 31 #define STM32MP_SYSRAM_SIZE U(0x00040000) 32 33 /* DDR configuration */ 34 #define STM32MP_DDR_BASE U(0xC0000000) 35 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 36 #define STM32MP_DDR_SPEED_DFLT 528 37 38 /* DDR power initializations */ 39 #ifndef __ASSEMBLY__ 40 enum ddr_type { 41 STM32MP_DDR3, 42 STM32MP_LPDDR2, 43 }; 44 #endif 45 46 /* Section used inside TF binaries */ 47 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 48 /* 256 Octets reserved for header */ 49 #define STM32MP_HEADER_SIZE U(0x00000100) 50 51 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 52 STM32MP_PARAM_LOAD_SIZE + \ 53 STM32MP_HEADER_SIZE) 54 55 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 56 (STM32MP_PARAM_LOAD_SIZE + \ 57 STM32MP_HEADER_SIZE)) 58 59 #if STACK_PROTECTOR_ENABLED 60 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 61 #else 62 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 63 #endif 64 65 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 66 STM32MP_SYSRAM_SIZE - \ 67 STM32MP_BL32_SIZE) 68 69 #if STACK_PROTECTOR_ENABLED 70 #define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 71 #else 72 #define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 73 #endif 74 75 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 76 STM32MP_BL2_SIZE) 77 78 /* BL2 and BL32/sp_min require 5 tables */ 79 #define MAX_XLAT_TABLES 5 80 81 /* 82 * MAX_MMAP_REGIONS is usually: 83 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 84 */ 85 #if defined(IMAGE_BL2) 86 #define MAX_MMAP_REGIONS 11 87 #endif 88 #if defined(IMAGE_BL32) 89 #define MAX_MMAP_REGIONS 6 90 #endif 91 92 /* DTB initialization value */ 93 #define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 94 95 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 96 STM32MP_DTB_SIZE) 97 98 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 99 100 /******************************************************************************* 101 * STM32MP1 device/io map related constants (used for MMU) 102 ******************************************************************************/ 103 #define STM32MP1_DEVICE1_BASE U(0x40000000) 104 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 105 106 #define STM32MP1_DEVICE2_BASE U(0x80000000) 107 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 108 109 /******************************************************************************* 110 * STM32MP1 RCC 111 ******************************************************************************/ 112 #define RCC_BASE U(0x50000000) 113 114 /******************************************************************************* 115 * STM32MP1 PWR 116 ******************************************************************************/ 117 #define PWR_BASE U(0x50001000) 118 119 /******************************************************************************* 120 * STM32MP1 GPIO 121 ******************************************************************************/ 122 #define GPIOA_BASE U(0x50002000) 123 #define GPIOB_BASE U(0x50003000) 124 #define GPIOC_BASE U(0x50004000) 125 #define GPIOD_BASE U(0x50005000) 126 #define GPIOE_BASE U(0x50006000) 127 #define GPIOF_BASE U(0x50007000) 128 #define GPIOG_BASE U(0x50008000) 129 #define GPIOH_BASE U(0x50009000) 130 #define GPIOI_BASE U(0x5000A000) 131 #define GPIOJ_BASE U(0x5000B000) 132 #define GPIOK_BASE U(0x5000C000) 133 #define GPIOZ_BASE U(0x54004000) 134 #define GPIO_BANK_OFFSET U(0x1000) 135 136 /* Bank IDs used in GPIO driver API */ 137 #define GPIO_BANK_A U(0) 138 #define GPIO_BANK_B U(1) 139 #define GPIO_BANK_C U(2) 140 #define GPIO_BANK_D U(3) 141 #define GPIO_BANK_E U(4) 142 #define GPIO_BANK_F U(5) 143 #define GPIO_BANK_G U(6) 144 #define GPIO_BANK_H U(7) 145 #define GPIO_BANK_I U(8) 146 #define GPIO_BANK_J U(9) 147 #define GPIO_BANK_K U(10) 148 #define GPIO_BANK_Z U(25) 149 150 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 151 152 /******************************************************************************* 153 * STM32MP1 UART 154 ******************************************************************************/ 155 #define USART1_BASE U(0x5C000000) 156 #define USART2_BASE U(0x4000E000) 157 #define USART3_BASE U(0x4000F000) 158 #define UART4_BASE U(0x40010000) 159 #define UART5_BASE U(0x40011000) 160 #define USART6_BASE U(0x44003000) 161 #define UART7_BASE U(0x40018000) 162 #define UART8_BASE U(0x40019000) 163 #define STM32MP_UART_BAUDRATE U(115200) 164 165 /* For UART crash console */ 166 #define STM32MP_DEBUG_USART_BASE UART4_BASE 167 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 168 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 169 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 170 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 171 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 172 #define DEBUG_UART_TX_GPIO_PORT 11 173 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 174 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 175 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 176 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 177 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 178 179 /******************************************************************************* 180 * STM32MP1 TZC (TZ400) 181 ******************************************************************************/ 182 #define STM32MP1_TZC_BASE U(0x5C006000) 183 184 #define STM32MP1_TZC_A7_ID U(0) 185 #define STM32MP1_TZC_LCD_ID U(3) 186 #define STM32MP1_TZC_GPU_ID U(4) 187 #define STM32MP1_TZC_MDMA_ID U(5) 188 #define STM32MP1_TZC_DMA_ID U(6) 189 #define STM32MP1_TZC_USB_HOST_ID U(7) 190 #define STM32MP1_TZC_USB_OTG_ID U(8) 191 #define STM32MP1_TZC_SDMMC_ID U(9) 192 #define STM32MP1_TZC_ETH_ID U(10) 193 #define STM32MP1_TZC_DAP_ID U(15) 194 195 #define STM32MP1_FILTER_BIT_ALL U(3) 196 197 /******************************************************************************* 198 * STM32MP1 SDMMC 199 ******************************************************************************/ 200 #define STM32MP_SDMMC1_BASE U(0x58005000) 201 #define STM32MP_SDMMC2_BASE U(0x58007000) 202 #define STM32MP_SDMMC3_BASE U(0x48004000) 203 204 #define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/ 205 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 206 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 207 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 208 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 209 210 /******************************************************************************* 211 * STM32MP1 BSEC / OTP 212 ******************************************************************************/ 213 #define STM32MP1_OTP_MAX_ID 0x5FU 214 #define STM32MP1_UPPER_OTP_START 0x20U 215 216 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 217 218 /* OTP offsets */ 219 #define DATA0_OTP U(0) 220 221 /* OTP mask */ 222 /* DATA0 */ 223 #define DATA0_OTP_SECURED BIT(6) 224 225 /******************************************************************************* 226 * STM32MP1 TAMP 227 ******************************************************************************/ 228 #define TAMP_BASE U(0x5C00A000) 229 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 230 231 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 232 static inline uint32_t tamp_bkpr(uint32_t idx) 233 { 234 return TAMP_BKP_REGISTER_BASE + (idx << 2); 235 } 236 #endif 237 238 /******************************************************************************* 239 * STM32MP1 DDRCTRL 240 ******************************************************************************/ 241 #define DDRCTRL_BASE U(0x5A003000) 242 243 /******************************************************************************* 244 * STM32MP1 DDRPHYC 245 ******************************************************************************/ 246 #define DDRPHYC_BASE U(0x5A004000) 247 248 /******************************************************************************* 249 * STM32MP1 I2C4 250 ******************************************************************************/ 251 #define I2C4_BASE U(0x5C002000) 252 253 #endif /* STM32MP1_DEF_H */ 254