1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 14 #ifndef __ASSEMBLY__ 15 #include <boot_api.h> 16 #include <stm32mp_common.h> 17 #include <stm32mp_dt.h> 18 #include <stm32mp1_private.h> 19 #endif 20 21 /******************************************************************************* 22 * STM32MP1 memory map related constants 23 ******************************************************************************/ 24 25 #define STM32MP1_SRAM_BASE U(0x2FFC0000) 26 #define STM32MP1_SRAM_SIZE U(0x00040000) 27 28 /* DDR configuration */ 29 #define STM32MP1_DDR_BASE U(0xC0000000) 30 #define STM32MP1_DDR_SIZE_DFLT U(0x20000000) /* 512 MB */ 31 #define STM32MP1_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 32 #define STM32MP1_DDR_SPEED_DFLT 528 33 34 /* DDR power initializations */ 35 #ifndef __ASSEMBLY__ 36 enum ddr_type { 37 STM32MP_DDR3, 38 STM32MP_LPDDR2, 39 }; 40 #endif 41 42 /* Section used inside TF binaries */ 43 #define STM32MP1_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 44 /* 256 Octets reserved for header */ 45 #define STM32MP1_HEADER_SIZE U(0x00000100) 46 47 #define STM32MP1_BINARY_BASE (STM32MP1_SRAM_BASE + \ 48 STM32MP1_PARAM_LOAD_SIZE + \ 49 STM32MP1_HEADER_SIZE) 50 51 #define STM32MP1_BINARY_SIZE (STM32MP1_SRAM_SIZE - \ 52 (STM32MP1_PARAM_LOAD_SIZE + \ 53 STM32MP1_HEADER_SIZE)) 54 55 #if STACK_PROTECTOR_ENABLED 56 #define STM32MP1_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 57 #else 58 #define STM32MP1_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 59 #endif 60 61 #define STM32MP1_BL32_BASE (STM32MP1_SRAM_BASE + \ 62 STM32MP1_SRAM_SIZE - \ 63 STM32MP1_BL32_SIZE) 64 65 #if STACK_PROTECTOR_ENABLED 66 #define STM32MP1_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 67 #else 68 #define STM32MP1_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 69 #endif 70 71 #define STM32MP1_BL2_BASE (STM32MP1_BL32_BASE - \ 72 STM32MP1_BL2_SIZE) 73 74 /* BL2 and BL32/sp_min require 5 tables */ 75 #define MAX_XLAT_TABLES 5 76 77 /* 78 * MAX_MMAP_REGIONS is usually: 79 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 80 */ 81 #if defined(IMAGE_BL2) 82 #define MAX_MMAP_REGIONS 11 83 #endif 84 #if defined(IMAGE_BL32) 85 #define MAX_MMAP_REGIONS 6 86 #endif 87 88 /* DTB initialization value */ 89 #define STM32MP1_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 90 91 #define STM32MP1_DTB_BASE (STM32MP1_BL2_BASE - \ 92 STM32MP1_DTB_SIZE) 93 94 #define STM32MP1_BL33_BASE (STM32MP1_DDR_BASE + U(0x100000)) 95 96 /******************************************************************************* 97 * STM32MP1 device/io map related constants (used for MMU) 98 ******************************************************************************/ 99 #define STM32MP1_DEVICE1_BASE U(0x40000000) 100 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 101 102 #define STM32MP1_DEVICE2_BASE U(0x80000000) 103 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 104 105 /******************************************************************************* 106 * STM32MP1 RCC 107 ******************************************************************************/ 108 #define RCC_BASE U(0x50000000) 109 110 /******************************************************************************* 111 * STM32MP1 PWR 112 ******************************************************************************/ 113 #define PWR_BASE U(0x50001000) 114 115 /******************************************************************************* 116 * STM32MP1 GPIO 117 ******************************************************************************/ 118 #define GPIOA_BASE U(0x50002000) 119 #define GPIOB_BASE U(0x50003000) 120 #define GPIOC_BASE U(0x50004000) 121 #define GPIOD_BASE U(0x50005000) 122 #define GPIOE_BASE U(0x50006000) 123 #define GPIOF_BASE U(0x50007000) 124 #define GPIOG_BASE U(0x50008000) 125 #define GPIOH_BASE U(0x50009000) 126 #define GPIOI_BASE U(0x5000A000) 127 #define GPIOJ_BASE U(0x5000B000) 128 #define GPIOK_BASE U(0x5000C000) 129 #define GPIOZ_BASE U(0x54004000) 130 #define GPIO_BANK_OFFSET U(0x1000) 131 132 /* Bank IDs used in GPIO driver API */ 133 #define GPIO_BANK_A U(0) 134 #define GPIO_BANK_B U(1) 135 #define GPIO_BANK_C U(2) 136 #define GPIO_BANK_D U(3) 137 #define GPIO_BANK_E U(4) 138 #define GPIO_BANK_F U(5) 139 #define GPIO_BANK_G U(6) 140 #define GPIO_BANK_H U(7) 141 #define GPIO_BANK_I U(8) 142 #define GPIO_BANK_J U(9) 143 #define GPIO_BANK_K U(10) 144 #define GPIO_BANK_Z U(25) 145 146 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 147 148 /******************************************************************************* 149 * STM32MP1 UART 150 ******************************************************************************/ 151 #define USART1_BASE U(0x5C000000) 152 #define USART2_BASE U(0x4000E000) 153 #define USART3_BASE U(0x4000F000) 154 #define UART4_BASE U(0x40010000) 155 #define UART5_BASE U(0x40011000) 156 #define USART6_BASE U(0x44003000) 157 #define UART7_BASE U(0x40018000) 158 #define UART8_BASE U(0x40019000) 159 #define STM32MP1_UART_BAUDRATE U(115200) 160 161 /* For UART crash console */ 162 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 163 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 164 #define STM32MP1_DEBUG_USART_CLK_FRQ 64000000 165 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 166 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 167 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 168 #define DEBUG_UART_TX_GPIO_PORT 11 169 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 170 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 171 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 172 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 173 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 174 175 /******************************************************************************* 176 * STM32MP1 TZC (TZ400) 177 ******************************************************************************/ 178 #define STM32MP1_TZC_BASE U(0x5C006000) 179 180 #define STM32MP1_TZC_A7_ID U(0) 181 #define STM32MP1_TZC_LCD_ID U(3) 182 #define STM32MP1_TZC_GPU_ID U(4) 183 #define STM32MP1_TZC_MDMA_ID U(5) 184 #define STM32MP1_TZC_DMA_ID U(6) 185 #define STM32MP1_TZC_USB_HOST_ID U(7) 186 #define STM32MP1_TZC_USB_OTG_ID U(8) 187 #define STM32MP1_TZC_SDMMC_ID U(9) 188 #define STM32MP1_TZC_ETH_ID U(10) 189 #define STM32MP1_TZC_DAP_ID U(15) 190 191 #define STM32MP1_FILTER_BIT_ALL U(3) 192 193 /******************************************************************************* 194 * STM32MP1 SDMMC 195 ******************************************************************************/ 196 #define STM32MP1_SDMMC1_BASE U(0x58005000) 197 #define STM32MP1_SDMMC2_BASE U(0x58007000) 198 #define STM32MP1_SDMMC3_BASE U(0x48004000) 199 200 #define STM32MP1_MMC_INIT_FREQ 400000 /*400 KHz*/ 201 #define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 202 #define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 203 #define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 204 #define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 205 206 /******************************************************************************* 207 * STM32MP1 BSEC / OTP 208 ******************************************************************************/ 209 #define STM32MP1_OTP_MAX_ID 0x5FU 210 #define STM32MP1_UPPER_OTP_START 0x20U 211 212 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 213 214 /* OTP offsets */ 215 #define DATA0_OTP U(0) 216 217 /* OTP mask */ 218 /* DATA0 */ 219 #define DATA0_OTP_SECURED BIT(6) 220 221 /******************************************************************************* 222 * STM32MP1 TAMP 223 ******************************************************************************/ 224 #define TAMP_BASE U(0x5C00A000) 225 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 226 227 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 228 static inline uint32_t tamp_bkpr(uint32_t idx) 229 { 230 return TAMP_BKP_REGISTER_BASE + (idx << 2); 231 } 232 #endif 233 234 /******************************************************************************* 235 * STM32MP1 DDRCTRL 236 ******************************************************************************/ 237 #define DDRCTRL_BASE U(0x5A003000) 238 239 /******************************************************************************* 240 * STM32MP1 DDRPHYC 241 ******************************************************************************/ 242 #define DDRPHYC_BASE U(0x5A004000) 243 244 /******************************************************************************* 245 * STM32MP1 I2C4 246 ******************************************************************************/ 247 #define I2C4_BASE U(0x5C002000) 248 249 #endif /* STM32MP1_DEF_H */ 250