1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_common.h> 23 #include <stm32mp_dt.h> 24 #include <stm32mp1_dbgmcu.h> 25 #include <stm32mp1_private.h> 26 #include <stm32mp1_shared_resources.h> 27 #endif 28 29 #if !STM32MP_USE_STM32IMAGE 30 #include "stm32mp1_fip_def.h" 31 #else /* STM32MP_USE_STM32IMAGE */ 32 #include "stm32mp1_stm32image_def.h" 33 #endif /* STM32MP_USE_STM32IMAGE */ 34 35 /******************************************************************************* 36 * CHIP ID 37 ******************************************************************************/ 38 #if STM32MP13 39 #define STM32MP1_CHIP_ID U(0x501) 40 41 #define STM32MP135C_PART_NB U(0x05010000) 42 #define STM32MP135A_PART_NB U(0x05010001) 43 #define STM32MP133C_PART_NB U(0x050100C0) 44 #define STM32MP133A_PART_NB U(0x050100C1) 45 #define STM32MP131C_PART_NB U(0x050106C8) 46 #define STM32MP131A_PART_NB U(0x050106C9) 47 #define STM32MP135F_PART_NB U(0x05010800) 48 #define STM32MP135D_PART_NB U(0x05010801) 49 #define STM32MP133F_PART_NB U(0x050108C0) 50 #define STM32MP133D_PART_NB U(0x050108C1) 51 #define STM32MP131F_PART_NB U(0x05010EC8) 52 #define STM32MP131D_PART_NB U(0x05010EC9) 53 #endif 54 #if STM32MP15 55 #define STM32MP1_CHIP_ID U(0x500) 56 57 #define STM32MP157C_PART_NB U(0x05000000) 58 #define STM32MP157A_PART_NB U(0x05000001) 59 #define STM32MP153C_PART_NB U(0x05000024) 60 #define STM32MP153A_PART_NB U(0x05000025) 61 #define STM32MP151C_PART_NB U(0x0500002E) 62 #define STM32MP151A_PART_NB U(0x0500002F) 63 #define STM32MP157F_PART_NB U(0x05000080) 64 #define STM32MP157D_PART_NB U(0x05000081) 65 #define STM32MP153F_PART_NB U(0x050000A4) 66 #define STM32MP153D_PART_NB U(0x050000A5) 67 #define STM32MP151F_PART_NB U(0x050000AE) 68 #define STM32MP151D_PART_NB U(0x050000AF) 69 #endif 70 71 #define STM32MP1_REV_B U(0x2000) 72 #if STM32MP13 73 #define STM32MP1_REV_Y U(0x1003) 74 #define STM32MP1_REV_Z U(0x1001) 75 #endif 76 #if STM32MP15 77 #define STM32MP1_REV_Z U(0x2001) 78 #endif 79 80 /******************************************************************************* 81 * PACKAGE ID 82 ******************************************************************************/ 83 #if STM32MP15 84 #define PKG_AA_LFBGA448 U(4) 85 #define PKG_AB_LFBGA354 U(3) 86 #define PKG_AC_TFBGA361 U(2) 87 #define PKG_AD_TFBGA257 U(1) 88 #endif 89 90 /******************************************************************************* 91 * STM32MP1 memory map related constants 92 ******************************************************************************/ 93 #define STM32MP_ROM_BASE U(0x00000000) 94 #define STM32MP_ROM_SIZE U(0x00020000) 95 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 96 97 #if STM32MP13 98 #define STM32MP_SYSRAM_BASE U(0x2FFE0000) 99 #define STM32MP_SYSRAM_SIZE U(0x00020000) 100 #define SRAM1_BASE U(0x30000000) 101 #define SRAM1_SIZE U(0x00004000) 102 #define SRAM2_BASE U(0x30004000) 103 #define SRAM2_SIZE U(0x00002000) 104 #define SRAM3_BASE U(0x30006000) 105 #define SRAM3_SIZE U(0x00002000) 106 #define SRAMS_BASE SRAM1_BASE 107 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000) 108 #endif /* STM32MP13 */ 109 #if STM32MP15 110 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 111 #define STM32MP_SYSRAM_SIZE U(0x00040000) 112 #endif /* STM32MP15 */ 113 114 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 115 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 116 STM32MP_SYSRAM_SIZE - \ 117 STM32MP_NS_SYSRAM_SIZE) 118 119 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 120 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 121 122 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 123 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 124 STM32MP_NS_SYSRAM_SIZE) 125 126 /* DDR configuration */ 127 #define STM32MP_DDR_BASE U(0xC0000000) 128 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 129 130 /* DDR power initializations */ 131 #ifndef __ASSEMBLER__ 132 enum ddr_type { 133 STM32MP_DDR3, 134 STM32MP_LPDDR2, 135 STM32MP_LPDDR3 136 }; 137 #endif 138 139 /* Section used inside TF binaries */ 140 #if STM32MP13 141 /* 512 Octets reserved for header */ 142 #define STM32MP_HEADER_RESERVED_SIZE U(0x200) 143 144 #define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE 145 146 #define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE 147 #endif 148 #if STM32MP15 149 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 150 /* 256 Octets reserved for header */ 151 #define STM32MP_HEADER_SIZE U(0x00000100) 152 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 153 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 154 155 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 156 STM32MP_PARAM_LOAD_SIZE + \ 157 STM32MP_HEADER_SIZE) 158 159 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 160 (STM32MP_PARAM_LOAD_SIZE + \ 161 STM32MP_HEADER_SIZE)) 162 #endif 163 164 /* BL2 and BL32/sp_min require finer granularity tables */ 165 #if defined(IMAGE_BL2) 166 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 167 #endif 168 169 #if defined(IMAGE_BL32) 170 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 171 #endif 172 173 /* 174 * MAX_MMAP_REGIONS is usually: 175 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 176 */ 177 #if defined(IMAGE_BL2) 178 #if STM32MP_USB_PROGRAMMER 179 #define MAX_MMAP_REGIONS 8 180 #else 181 #define MAX_MMAP_REGIONS 7 182 #endif 183 #endif 184 185 #if STM32MP13 186 #define STM32MP_BL33_BASE STM32MP_DDR_BASE 187 #endif 188 #if STM32MP15 189 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 190 #endif 191 #define STM32MP_BL33_MAX_SIZE U(0x400000) 192 193 /* Define maximum page size for NAND devices */ 194 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 195 196 /* Define location for the MTD scratch buffer */ 197 #if STM32MP13 198 #define STM32MP_MTD_BUFFER (SRAM1_BASE + \ 199 SRAM1_SIZE - \ 200 PLATFORM_MTD_MAX_PAGE_SIZE) 201 #endif 202 /******************************************************************************* 203 * STM32MP1 device/io map related constants (used for MMU) 204 ******************************************************************************/ 205 #define STM32MP1_DEVICE1_BASE U(0x40000000) 206 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 207 208 #define STM32MP1_DEVICE2_BASE U(0x80000000) 209 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 210 211 /******************************************************************************* 212 * STM32MP1 RCC 213 ******************************************************************************/ 214 #define RCC_BASE U(0x50000000) 215 216 /******************************************************************************* 217 * STM32MP1 PWR 218 ******************************************************************************/ 219 #define PWR_BASE U(0x50001000) 220 221 /******************************************************************************* 222 * STM32MP1 GPIO 223 ******************************************************************************/ 224 #define GPIOA_BASE U(0x50002000) 225 #define GPIOB_BASE U(0x50003000) 226 #define GPIOC_BASE U(0x50004000) 227 #define GPIOD_BASE U(0x50005000) 228 #define GPIOE_BASE U(0x50006000) 229 #define GPIOF_BASE U(0x50007000) 230 #define GPIOG_BASE U(0x50008000) 231 #define GPIOH_BASE U(0x50009000) 232 #define GPIOI_BASE U(0x5000A000) 233 #if STM32MP15 234 #define GPIOJ_BASE U(0x5000B000) 235 #define GPIOK_BASE U(0x5000C000) 236 #define GPIOZ_BASE U(0x54004000) 237 #endif 238 #define GPIO_BANK_OFFSET U(0x1000) 239 240 /* Bank IDs used in GPIO driver API */ 241 #define GPIO_BANK_A U(0) 242 #define GPIO_BANK_B U(1) 243 #define GPIO_BANK_C U(2) 244 #define GPIO_BANK_D U(3) 245 #define GPIO_BANK_E U(4) 246 #define GPIO_BANK_F U(5) 247 #define GPIO_BANK_G U(6) 248 #define GPIO_BANK_H U(7) 249 #define GPIO_BANK_I U(8) 250 #if STM32MP15 251 #define GPIO_BANK_J U(9) 252 #define GPIO_BANK_K U(10) 253 #define GPIO_BANK_Z U(25) 254 255 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 256 #endif 257 258 /******************************************************************************* 259 * STM32MP1 UART 260 ******************************************************************************/ 261 #if STM32MP13 262 #define USART1_BASE U(0x4C000000) 263 #define USART2_BASE U(0x4C001000) 264 #endif 265 #if STM32MP15 266 #define USART1_BASE U(0x5C000000) 267 #define USART2_BASE U(0x4000E000) 268 #endif 269 #define USART3_BASE U(0x4000F000) 270 #define UART4_BASE U(0x40010000) 271 #define UART5_BASE U(0x40011000) 272 #define USART6_BASE U(0x44003000) 273 #define UART7_BASE U(0x40018000) 274 #define UART8_BASE U(0x40019000) 275 276 /* For UART crash console */ 277 #define STM32MP_DEBUG_USART_BASE UART4_BASE 278 #if STM32MP13 279 /* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */ 280 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 281 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE 282 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR 283 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN 284 #define DEBUG_UART_TX_GPIO_PORT 6 285 #define DEBUG_UART_TX_GPIO_ALTERNATE 8 286 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR 287 #define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI 288 #endif /* STM32MP13 */ 289 #if STM32MP15 290 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 291 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 292 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 293 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 294 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 295 #define DEBUG_UART_TX_GPIO_PORT 11 296 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 297 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 298 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 299 #endif /* STM32MP15 */ 300 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 301 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 302 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 303 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 304 305 /******************************************************************************* 306 * STM32MP1 ETZPC 307 ******************************************************************************/ 308 #define STM32MP1_ETZPC_BASE U(0x5C007000) 309 310 /* ETZPC TZMA IDs */ 311 #define STM32MP1_ETZPC_TZMA_ROM U(0) 312 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 313 314 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 315 316 /* ETZPC DECPROT IDs */ 317 #define STM32MP1_ETZPC_STGENC_ID 0 318 #define STM32MP1_ETZPC_BKPSRAM_ID 1 319 #define STM32MP1_ETZPC_IWDG1_ID 2 320 #define STM32MP1_ETZPC_USART1_ID 3 321 #define STM32MP1_ETZPC_SPI6_ID 4 322 #define STM32MP1_ETZPC_I2C4_ID 5 323 #define STM32MP1_ETZPC_RNG1_ID 7 324 #define STM32MP1_ETZPC_HASH1_ID 8 325 #define STM32MP1_ETZPC_CRYP1_ID 9 326 #define STM32MP1_ETZPC_DDRCTRL_ID 10 327 #define STM32MP1_ETZPC_DDRPHYC_ID 11 328 #define STM32MP1_ETZPC_I2C6_ID 12 329 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 330 331 #define STM32MP1_ETZPC_TIM2_ID 16 332 #define STM32MP1_ETZPC_TIM3_ID 17 333 #define STM32MP1_ETZPC_TIM4_ID 18 334 #define STM32MP1_ETZPC_TIM5_ID 19 335 #define STM32MP1_ETZPC_TIM6_ID 20 336 #define STM32MP1_ETZPC_TIM7_ID 21 337 #define STM32MP1_ETZPC_TIM12_ID 22 338 #define STM32MP1_ETZPC_TIM13_ID 23 339 #define STM32MP1_ETZPC_TIM14_ID 24 340 #define STM32MP1_ETZPC_LPTIM1_ID 25 341 #define STM32MP1_ETZPC_WWDG1_ID 26 342 #define STM32MP1_ETZPC_SPI2_ID 27 343 #define STM32MP1_ETZPC_SPI3_ID 28 344 #define STM32MP1_ETZPC_SPDIFRX_ID 29 345 #define STM32MP1_ETZPC_USART2_ID 30 346 #define STM32MP1_ETZPC_USART3_ID 31 347 #define STM32MP1_ETZPC_UART4_ID 32 348 #define STM32MP1_ETZPC_UART5_ID 33 349 #define STM32MP1_ETZPC_I2C1_ID 34 350 #define STM32MP1_ETZPC_I2C2_ID 35 351 #define STM32MP1_ETZPC_I2C3_ID 36 352 #define STM32MP1_ETZPC_I2C5_ID 37 353 #define STM32MP1_ETZPC_CEC_ID 38 354 #define STM32MP1_ETZPC_DAC_ID 39 355 #define STM32MP1_ETZPC_UART7_ID 40 356 #define STM32MP1_ETZPC_UART8_ID 41 357 #define STM32MP1_ETZPC_MDIOS_ID 44 358 #define STM32MP1_ETZPC_TIM1_ID 48 359 #define STM32MP1_ETZPC_TIM8_ID 49 360 #define STM32MP1_ETZPC_USART6_ID 51 361 #define STM32MP1_ETZPC_SPI1_ID 52 362 #define STM32MP1_ETZPC_SPI4_ID 53 363 #define STM32MP1_ETZPC_TIM15_ID 54 364 #define STM32MP1_ETZPC_TIM16_ID 55 365 #define STM32MP1_ETZPC_TIM17_ID 56 366 #define STM32MP1_ETZPC_SPI5_ID 57 367 #define STM32MP1_ETZPC_SAI1_ID 58 368 #define STM32MP1_ETZPC_SAI2_ID 59 369 #define STM32MP1_ETZPC_SAI3_ID 60 370 #define STM32MP1_ETZPC_DFSDM_ID 61 371 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 372 #define STM32MP1_ETZPC_LPTIM2_ID 64 373 #define STM32MP1_ETZPC_LPTIM3_ID 65 374 #define STM32MP1_ETZPC_LPTIM4_ID 66 375 #define STM32MP1_ETZPC_LPTIM5_ID 67 376 #define STM32MP1_ETZPC_SAI4_ID 68 377 #define STM32MP1_ETZPC_VREFBUF_ID 69 378 #define STM32MP1_ETZPC_DCMI_ID 70 379 #define STM32MP1_ETZPC_CRC2_ID 71 380 #define STM32MP1_ETZPC_ADC_ID 72 381 #define STM32MP1_ETZPC_HASH2_ID 73 382 #define STM32MP1_ETZPC_RNG2_ID 74 383 #define STM32MP1_ETZPC_CRYP2_ID 75 384 #define STM32MP1_ETZPC_SRAM1_ID 80 385 #define STM32MP1_ETZPC_SRAM2_ID 81 386 #define STM32MP1_ETZPC_SRAM3_ID 82 387 #define STM32MP1_ETZPC_SRAM4_ID 83 388 #define STM32MP1_ETZPC_RETRAM_ID 84 389 #define STM32MP1_ETZPC_OTG_ID 85 390 #define STM32MP1_ETZPC_SDMMC3_ID 86 391 #define STM32MP1_ETZPC_DLYBSD3_ID 87 392 #define STM32MP1_ETZPC_DMA1_ID 88 393 #define STM32MP1_ETZPC_DMA2_ID 89 394 #define STM32MP1_ETZPC_DMAMUX_ID 90 395 #define STM32MP1_ETZPC_FMC_ID 91 396 #define STM32MP1_ETZPC_QSPI_ID 92 397 #define STM32MP1_ETZPC_DLYBQ_ID 93 398 #define STM32MP1_ETZPC_ETH_ID 94 399 #define STM32MP1_ETZPC_RSV_ID 95 400 401 #define STM32MP_ETZPC_MAX_ID 96 402 403 /******************************************************************************* 404 * STM32MP1 TZC (TZ400) 405 ******************************************************************************/ 406 #define STM32MP1_TZC_BASE U(0x5C006000) 407 408 #if STM32MP13 409 #define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0) 410 #endif 411 #if STM32MP15 412 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 413 TZC_400_REGION_ATTR_FILTER_BIT(1)) 414 #endif 415 416 /******************************************************************************* 417 * STM32MP1 SDMMC 418 ******************************************************************************/ 419 #define STM32MP_SDMMC1_BASE U(0x58005000) 420 #define STM32MP_SDMMC2_BASE U(0x58007000) 421 #define STM32MP_SDMMC3_BASE U(0x48004000) 422 423 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 424 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 425 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 426 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 427 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 428 429 /******************************************************************************* 430 * STM32MP1 BSEC / OTP 431 ******************************************************************************/ 432 #define STM32MP1_OTP_MAX_ID 0x5FU 433 #define STM32MP1_UPPER_OTP_START 0x20U 434 435 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 436 437 /* OTP labels */ 438 #define CFG0_OTP "cfg0_otp" 439 #define PART_NUMBER_OTP "part_number_otp" 440 #if STM32MP15 441 #define PACKAGE_OTP "package_otp" 442 #endif 443 #define HW2_OTP "hw2_otp" 444 #if STM32MP13 445 #define NAND_OTP "cfg9_otp" 446 #define NAND2_OTP "cfg10_otp" 447 #endif 448 #if STM32MP15 449 #define NAND_OTP "nand_otp" 450 #endif 451 #define MONOTONIC_OTP "monotonic_otp" 452 #define UID_OTP "uid_otp" 453 #define PKH_OTP "pkh_otp" 454 #define ENCKEY_OTP "enckey_otp" 455 #define BOARD_ID_OTP "board_id" 456 457 /* OTP mask */ 458 /* CFG0 */ 459 #if STM32MP13 460 #define CFG0_OTP_MODE_MASK GENMASK_32(9, 0) 461 #define CFG0_OTP_MODE_SHIFT 0 462 #define CFG0_OPEN_DEVICE 0x17U 463 #define CFG0_CLOSED_DEVICE 0x3FU 464 #define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU 465 #define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU 466 #endif 467 #if STM32MP15 468 #define CFG0_CLOSED_DEVICE BIT(6) 469 #endif 470 471 /* PART NUMBER */ 472 #if STM32MP13 473 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0) 474 #endif 475 #if STM32MP15 476 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 477 #endif 478 #define PART_NUMBER_OTP_PART_SHIFT 0 479 480 /* PACKAGE */ 481 #if STM32MP15 482 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 483 #define PACKAGE_OTP_PKG_SHIFT 27 484 #endif 485 486 /* IWDG OTP */ 487 #define HW2_OTP_IWDG_HW_POS U(3) 488 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 489 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 490 491 /* HW2 OTP */ 492 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 493 494 /* NAND OTP */ 495 /* NAND parameter storage flag */ 496 #define NAND_PARAM_STORED_IN_OTP BIT(31) 497 498 /* NAND page size in bytes */ 499 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 500 #define NAND_PAGE_SIZE_SHIFT 29 501 #define NAND_PAGE_SIZE_2K U(0) 502 #define NAND_PAGE_SIZE_4K U(1) 503 #define NAND_PAGE_SIZE_8K U(2) 504 505 /* NAND block size in pages */ 506 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 507 #define NAND_BLOCK_SIZE_SHIFT 27 508 #define NAND_BLOCK_SIZE_64_PAGES U(0) 509 #define NAND_BLOCK_SIZE_128_PAGES U(1) 510 #define NAND_BLOCK_SIZE_256_PAGES U(2) 511 512 /* NAND number of block (in unit of 256 blocks) */ 513 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 514 #define NAND_BLOCK_NB_SHIFT 19 515 #define NAND_BLOCK_NB_UNIT U(256) 516 517 /* NAND bus width in bits */ 518 #define NAND_WIDTH_MASK BIT(18) 519 #define NAND_WIDTH_SHIFT 18 520 521 /* NAND number of ECC bits per 512 bytes */ 522 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 523 #define NAND_ECC_BIT_NB_SHIFT 15 524 #define NAND_ECC_BIT_NB_UNSET U(0) 525 #define NAND_ECC_BIT_NB_1_BITS U(1) 526 #define NAND_ECC_BIT_NB_4_BITS U(2) 527 #define NAND_ECC_BIT_NB_8_BITS U(3) 528 #define NAND_ECC_ON_DIE U(4) 529 530 /* NAND number of planes */ 531 #define NAND_PLANE_BIT_NB_MASK BIT(14) 532 533 /* NAND2 OTP */ 534 #define NAND2_PAGE_SIZE_SHIFT 16 535 536 /* NAND2 config distribution */ 537 #define NAND2_CONFIG_DISTRIB BIT(0) 538 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 539 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 540 541 /* MONOTONIC OTP */ 542 #define MAX_MONOTONIC_VALUE 32 543 544 /* UID OTP */ 545 #define UID_WORD_NB U(3) 546 547 /* FWU configuration (max supported value is 15) */ 548 #define FWU_MAX_TRIAL_REBOOT U(3) 549 550 /******************************************************************************* 551 * STM32MP1 TAMP 552 ******************************************************************************/ 553 #define TAMP_BASE U(0x5C00A000) 554 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 555 #define TAMP_COUNTR U(0x40) 556 557 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 558 static inline uintptr_t tamp_bkpr(uint32_t idx) 559 { 560 return TAMP_BKP_REGISTER_BASE + (idx << 2); 561 } 562 #endif 563 564 /******************************************************************************* 565 * STM32MP1 USB 566 ******************************************************************************/ 567 #define USB_OTG_BASE U(0x49000000) 568 569 /******************************************************************************* 570 * STM32MP1 DDRCTRL 571 ******************************************************************************/ 572 #define DDRCTRL_BASE U(0x5A003000) 573 574 /******************************************************************************* 575 * STM32MP1 DDRPHYC 576 ******************************************************************************/ 577 #define DDRPHYC_BASE U(0x5A004000) 578 579 /******************************************************************************* 580 * STM32MP1 IWDG 581 ******************************************************************************/ 582 #define IWDG_MAX_INSTANCE U(2) 583 #define IWDG1_INST U(0) 584 #define IWDG2_INST U(1) 585 586 #define IWDG1_BASE U(0x5C003000) 587 #define IWDG2_BASE U(0x5A002000) 588 589 /******************************************************************************* 590 * Miscellaneous STM32MP1 peripherals base address 591 ******************************************************************************/ 592 #define BSEC_BASE U(0x5C005000) 593 #if STM32MP13 594 #define CRYP_BASE U(0x54002000) 595 #endif 596 #if STM32MP15 597 #define CRYP1_BASE U(0x54001000) 598 #endif 599 #define DBGMCU_BASE U(0x50081000) 600 #if STM32MP13 601 #define HASH_BASE U(0x54003000) 602 #endif 603 #if STM32MP15 604 #define HASH1_BASE U(0x54002000) 605 #endif 606 #if STM32MP13 607 #define I2C3_BASE U(0x4C004000) 608 #define I2C4_BASE U(0x4C005000) 609 #define I2C5_BASE U(0x4C006000) 610 #endif 611 #if STM32MP15 612 #define I2C4_BASE U(0x5C002000) 613 #define I2C6_BASE U(0x5c009000) 614 #endif 615 #if STM32MP13 616 #define RNG_BASE U(0x54004000) 617 #endif 618 #if STM32MP15 619 #define RNG1_BASE U(0x54003000) 620 #endif 621 #define RTC_BASE U(0x5c004000) 622 #if STM32MP13 623 #define SPI4_BASE U(0x4C002000) 624 #define SPI5_BASE U(0x4C003000) 625 #endif 626 #if STM32MP15 627 #define SPI6_BASE U(0x5c001000) 628 #endif 629 #define STGEN_BASE U(0x5c008000) 630 #define SYSCFG_BASE U(0x50020000) 631 632 /******************************************************************************* 633 * STM32MP13 SAES 634 ******************************************************************************/ 635 #define SAES_BASE U(0x54005000) 636 637 /******************************************************************************* 638 * STM32MP13 PKA 639 ******************************************************************************/ 640 #define PKA_BASE U(0x54006000) 641 642 /******************************************************************************* 643 * REGULATORS 644 ******************************************************************************/ 645 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 646 #define PLAT_NB_RDEVS U(19) 647 /* 2 FIXED */ 648 #define PLAT_NB_FIXED_REGS U(2) 649 650 /******************************************************************************* 651 * Device Tree defines 652 ******************************************************************************/ 653 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 654 #if STM32MP13 655 #define DT_DDR_COMPAT "st,stm32mp13-ddr" 656 #endif 657 #if STM32MP15 658 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 659 #endif 660 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 661 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 662 #if STM32MP13 663 #define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc" 664 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure" 665 #endif 666 #if STM32MP15 667 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 668 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 669 #endif 670 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 671 #define DT_UART_COMPAT "st,stm32h7-uart" 672 673 #endif /* STM32MP1_DEF_H */ 674