1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #include <stm32mp1_shared_resources.h> 29 #endif 30 31 /******************************************************************************* 32 * CHIP ID 33 ******************************************************************************/ 34 #define STM32MP157C_PART_NB U(0x05000000) 35 #define STM32MP157A_PART_NB U(0x05000001) 36 #define STM32MP153C_PART_NB U(0x05000024) 37 #define STM32MP153A_PART_NB U(0x05000025) 38 #define STM32MP151C_PART_NB U(0x0500002E) 39 #define STM32MP151A_PART_NB U(0x0500002F) 40 41 #define STM32MP1_REV_B U(0x2000) 42 43 /******************************************************************************* 44 * PACKAGE ID 45 ******************************************************************************/ 46 #define PKG_AA_LFBGA448 U(4) 47 #define PKG_AB_LFBGA354 U(3) 48 #define PKG_AC_TFBGA361 U(2) 49 #define PKG_AD_TFBGA257 U(1) 50 51 /******************************************************************************* 52 * STM32MP1 memory map related constants 53 ******************************************************************************/ 54 #define STM32MP_ROM_BASE U(0x00000000) 55 #define STM32MP_ROM_SIZE U(0x00020000) 56 57 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 58 #define STM32MP_SYSRAM_SIZE U(0x00040000) 59 60 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 61 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 62 STM32MP_SYSRAM_SIZE - \ 63 STM32MP_NS_SYSRAM_SIZE) 64 65 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 66 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 67 68 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 69 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 70 STM32MP_NS_SYSRAM_SIZE) 71 72 /* DDR configuration */ 73 #define STM32MP_DDR_BASE U(0xC0000000) 74 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 75 #ifdef AARCH32_SP_OPTEE 76 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 77 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 78 #else 79 #define STM32MP_DDR_S_SIZE U(0) 80 #define STM32MP_DDR_SHMEM_SIZE U(0) 81 #endif 82 83 /* DDR power initializations */ 84 #ifndef __ASSEMBLER__ 85 enum ddr_type { 86 STM32MP_DDR3, 87 STM32MP_LPDDR2, 88 STM32MP_LPDDR3 89 }; 90 #endif 91 92 /* Section used inside TF binaries */ 93 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 94 /* 256 Octets reserved for header */ 95 #define STM32MP_HEADER_SIZE U(0x00000100) 96 97 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 98 STM32MP_PARAM_LOAD_SIZE + \ 99 STM32MP_HEADER_SIZE) 100 101 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 102 (STM32MP_PARAM_LOAD_SIZE + \ 103 STM32MP_HEADER_SIZE)) 104 105 #ifdef AARCH32_SP_OPTEE 106 #define STM32MP_BL32_SIZE U(0) 107 108 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 109 110 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 111 STM32MP_OPTEE_BASE) 112 #else 113 #if STACK_PROTECTOR_ENABLED 114 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 115 #else 116 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 117 #endif 118 #endif 119 120 #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ 121 STM32MP_SEC_SYSRAM_SIZE - \ 122 STM32MP_BL32_SIZE) 123 124 #ifdef AARCH32_SP_OPTEE 125 #if STACK_PROTECTOR_ENABLED 126 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 127 #else 128 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 129 #endif 130 #else 131 #if STACK_PROTECTOR_ENABLED 132 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 133 #else 134 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 135 #endif 136 #endif 137 138 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 139 STM32MP_BL2_SIZE) 140 141 /* BL2 and BL32/sp_min require 4 tables */ 142 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 143 144 /* 145 * MAX_MMAP_REGIONS is usually: 146 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 147 */ 148 #if defined(IMAGE_BL2) 149 #define MAX_MMAP_REGIONS 11 150 #endif 151 #if defined(IMAGE_BL32) 152 #define MAX_MMAP_REGIONS 6 153 #endif 154 155 /* DTB initialization value */ 156 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 157 158 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 159 STM32MP_DTB_SIZE) 160 161 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 162 163 /* Define maximum page size for NAND devices */ 164 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 165 166 /******************************************************************************* 167 * STM32MP1 RAW partition offset for MTD devices 168 ******************************************************************************/ 169 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 170 #ifdef AARCH32_SP_OPTEE 171 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 172 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 173 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 174 #endif 175 176 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 177 #ifdef AARCH32_SP_OPTEE 178 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 179 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 180 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 181 #endif 182 183 /******************************************************************************* 184 * STM32MP1 device/io map related constants (used for MMU) 185 ******************************************************************************/ 186 #define STM32MP1_DEVICE1_BASE U(0x40000000) 187 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 188 189 #define STM32MP1_DEVICE2_BASE U(0x80000000) 190 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 191 192 /******************************************************************************* 193 * STM32MP1 RCC 194 ******************************************************************************/ 195 #define RCC_BASE U(0x50000000) 196 197 /******************************************************************************* 198 * STM32MP1 PWR 199 ******************************************************************************/ 200 #define PWR_BASE U(0x50001000) 201 202 /******************************************************************************* 203 * STM32MP1 GPIO 204 ******************************************************************************/ 205 #define GPIOA_BASE U(0x50002000) 206 #define GPIOB_BASE U(0x50003000) 207 #define GPIOC_BASE U(0x50004000) 208 #define GPIOD_BASE U(0x50005000) 209 #define GPIOE_BASE U(0x50006000) 210 #define GPIOF_BASE U(0x50007000) 211 #define GPIOG_BASE U(0x50008000) 212 #define GPIOH_BASE U(0x50009000) 213 #define GPIOI_BASE U(0x5000A000) 214 #define GPIOJ_BASE U(0x5000B000) 215 #define GPIOK_BASE U(0x5000C000) 216 #define GPIOZ_BASE U(0x54004000) 217 #define GPIO_BANK_OFFSET U(0x1000) 218 219 /* Bank IDs used in GPIO driver API */ 220 #define GPIO_BANK_A U(0) 221 #define GPIO_BANK_B U(1) 222 #define GPIO_BANK_C U(2) 223 #define GPIO_BANK_D U(3) 224 #define GPIO_BANK_E U(4) 225 #define GPIO_BANK_F U(5) 226 #define GPIO_BANK_G U(6) 227 #define GPIO_BANK_H U(7) 228 #define GPIO_BANK_I U(8) 229 #define GPIO_BANK_J U(9) 230 #define GPIO_BANK_K U(10) 231 #define GPIO_BANK_Z U(25) 232 233 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 234 235 /******************************************************************************* 236 * STM32MP1 UART 237 ******************************************************************************/ 238 #define USART1_BASE U(0x5C000000) 239 #define USART2_BASE U(0x4000E000) 240 #define USART3_BASE U(0x4000F000) 241 #define UART4_BASE U(0x40010000) 242 #define UART5_BASE U(0x40011000) 243 #define USART6_BASE U(0x44003000) 244 #define UART7_BASE U(0x40018000) 245 #define UART8_BASE U(0x40019000) 246 #define STM32MP_UART_BAUDRATE U(115200) 247 248 /* For UART crash console */ 249 #define STM32MP_DEBUG_USART_BASE UART4_BASE 250 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 251 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 252 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 253 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 254 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 255 #define DEBUG_UART_TX_GPIO_PORT 11 256 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 257 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 258 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 259 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 260 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 261 262 /******************************************************************************* 263 * STM32MP1 ETZPC 264 ******************************************************************************/ 265 #define STM32MP1_ETZPC_BASE U(0x5C007000) 266 267 /* ETZPC TZMA IDs */ 268 #define STM32MP1_ETZPC_TZMA_ROM U(0) 269 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 270 271 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 272 273 /* ETZPC DECPROT IDs */ 274 #define STM32MP1_ETZPC_STGENC_ID 0 275 #define STM32MP1_ETZPC_BKPSRAM_ID 1 276 #define STM32MP1_ETZPC_IWDG1_ID 2 277 #define STM32MP1_ETZPC_USART1_ID 3 278 #define STM32MP1_ETZPC_SPI6_ID 4 279 #define STM32MP1_ETZPC_I2C4_ID 5 280 #define STM32MP1_ETZPC_RNG1_ID 7 281 #define STM32MP1_ETZPC_HASH1_ID 8 282 #define STM32MP1_ETZPC_CRYP1_ID 9 283 #define STM32MP1_ETZPC_DDRCTRL_ID 10 284 #define STM32MP1_ETZPC_DDRPHYC_ID 11 285 #define STM32MP1_ETZPC_I2C6_ID 12 286 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 287 288 #define STM32MP1_ETZPC_TIM2_ID 16 289 #define STM32MP1_ETZPC_TIM3_ID 17 290 #define STM32MP1_ETZPC_TIM4_ID 18 291 #define STM32MP1_ETZPC_TIM5_ID 19 292 #define STM32MP1_ETZPC_TIM6_ID 20 293 #define STM32MP1_ETZPC_TIM7_ID 21 294 #define STM32MP1_ETZPC_TIM12_ID 22 295 #define STM32MP1_ETZPC_TIM13_ID 23 296 #define STM32MP1_ETZPC_TIM14_ID 24 297 #define STM32MP1_ETZPC_LPTIM1_ID 25 298 #define STM32MP1_ETZPC_WWDG1_ID 26 299 #define STM32MP1_ETZPC_SPI2_ID 27 300 #define STM32MP1_ETZPC_SPI3_ID 28 301 #define STM32MP1_ETZPC_SPDIFRX_ID 29 302 #define STM32MP1_ETZPC_USART2_ID 30 303 #define STM32MP1_ETZPC_USART3_ID 31 304 #define STM32MP1_ETZPC_UART4_ID 32 305 #define STM32MP1_ETZPC_UART5_ID 33 306 #define STM32MP1_ETZPC_I2C1_ID 34 307 #define STM32MP1_ETZPC_I2C2_ID 35 308 #define STM32MP1_ETZPC_I2C3_ID 36 309 #define STM32MP1_ETZPC_I2C5_ID 37 310 #define STM32MP1_ETZPC_CEC_ID 38 311 #define STM32MP1_ETZPC_DAC_ID 39 312 #define STM32MP1_ETZPC_UART7_ID 40 313 #define STM32MP1_ETZPC_UART8_ID 41 314 #define STM32MP1_ETZPC_MDIOS_ID 44 315 #define STM32MP1_ETZPC_TIM1_ID 48 316 #define STM32MP1_ETZPC_TIM8_ID 49 317 #define STM32MP1_ETZPC_USART6_ID 51 318 #define STM32MP1_ETZPC_SPI1_ID 52 319 #define STM32MP1_ETZPC_SPI4_ID 53 320 #define STM32MP1_ETZPC_TIM15_ID 54 321 #define STM32MP1_ETZPC_TIM16_ID 55 322 #define STM32MP1_ETZPC_TIM17_ID 56 323 #define STM32MP1_ETZPC_SPI5_ID 57 324 #define STM32MP1_ETZPC_SAI1_ID 58 325 #define STM32MP1_ETZPC_SAI2_ID 59 326 #define STM32MP1_ETZPC_SAI3_ID 60 327 #define STM32MP1_ETZPC_DFSDM_ID 61 328 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 329 #define STM32MP1_ETZPC_LPTIM2_ID 64 330 #define STM32MP1_ETZPC_LPTIM3_ID 65 331 #define STM32MP1_ETZPC_LPTIM4_ID 66 332 #define STM32MP1_ETZPC_LPTIM5_ID 67 333 #define STM32MP1_ETZPC_SAI4_ID 68 334 #define STM32MP1_ETZPC_VREFBUF_ID 69 335 #define STM32MP1_ETZPC_DCMI_ID 70 336 #define STM32MP1_ETZPC_CRC2_ID 71 337 #define STM32MP1_ETZPC_ADC_ID 72 338 #define STM32MP1_ETZPC_HASH2_ID 73 339 #define STM32MP1_ETZPC_RNG2_ID 74 340 #define STM32MP1_ETZPC_CRYP2_ID 75 341 #define STM32MP1_ETZPC_SRAM1_ID 80 342 #define STM32MP1_ETZPC_SRAM2_ID 81 343 #define STM32MP1_ETZPC_SRAM3_ID 82 344 #define STM32MP1_ETZPC_SRAM4_ID 83 345 #define STM32MP1_ETZPC_RETRAM_ID 84 346 #define STM32MP1_ETZPC_OTG_ID 85 347 #define STM32MP1_ETZPC_SDMMC3_ID 86 348 #define STM32MP1_ETZPC_DLYBSD3_ID 87 349 #define STM32MP1_ETZPC_DMA1_ID 88 350 #define STM32MP1_ETZPC_DMA2_ID 89 351 #define STM32MP1_ETZPC_DMAMUX_ID 90 352 #define STM32MP1_ETZPC_FMC_ID 91 353 #define STM32MP1_ETZPC_QSPI_ID 92 354 #define STM32MP1_ETZPC_DLYBQ_ID 93 355 #define STM32MP1_ETZPC_ETH_ID 94 356 #define STM32MP1_ETZPC_RSV_ID 95 357 358 #define STM32MP_ETZPC_MAX_ID 96 359 360 /******************************************************************************* 361 * STM32MP1 TZC (TZ400) 362 ******************************************************************************/ 363 #define STM32MP1_TZC_BASE U(0x5C006000) 364 365 #define STM32MP1_TZC_A7_ID U(0) 366 #define STM32MP1_TZC_M4_ID U(1) 367 #define STM32MP1_TZC_LCD_ID U(3) 368 #define STM32MP1_TZC_GPU_ID U(4) 369 #define STM32MP1_TZC_MDMA_ID U(5) 370 #define STM32MP1_TZC_DMA_ID U(6) 371 #define STM32MP1_TZC_USB_HOST_ID U(7) 372 #define STM32MP1_TZC_USB_OTG_ID U(8) 373 #define STM32MP1_TZC_SDMMC_ID U(9) 374 #define STM32MP1_TZC_ETH_ID U(10) 375 #define STM32MP1_TZC_DAP_ID U(15) 376 377 #define STM32MP1_FILTER_BIT_ALL U(3) 378 379 /******************************************************************************* 380 * STM32MP1 SDMMC 381 ******************************************************************************/ 382 #define STM32MP_SDMMC1_BASE U(0x58005000) 383 #define STM32MP_SDMMC2_BASE U(0x58007000) 384 #define STM32MP_SDMMC3_BASE U(0x48004000) 385 386 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 387 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 388 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 389 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 390 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 391 392 /******************************************************************************* 393 * STM32MP1 BSEC / OTP 394 ******************************************************************************/ 395 #define STM32MP1_OTP_MAX_ID 0x5FU 396 #define STM32MP1_UPPER_OTP_START 0x20U 397 398 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 399 400 /* OTP offsets */ 401 #define DATA0_OTP U(0) 402 #define PART_NUMBER_OTP U(1) 403 #define NAND_OTP U(9) 404 #define PACKAGE_OTP U(16) 405 #define HW2_OTP U(18) 406 407 /* OTP mask */ 408 /* DATA0 */ 409 #define DATA0_OTP_SECURED BIT(6) 410 411 /* PART NUMBER */ 412 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 413 #define PART_NUMBER_OTP_PART_SHIFT 0 414 415 /* PACKAGE */ 416 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 417 #define PACKAGE_OTP_PKG_SHIFT 27 418 419 /* IWDG OTP */ 420 #define HW2_OTP_IWDG_HW_POS U(3) 421 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 422 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 423 424 /* HW2 OTP */ 425 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 426 427 /* NAND OTP */ 428 /* NAND parameter storage flag */ 429 #define NAND_PARAM_STORED_IN_OTP BIT(31) 430 431 /* NAND page size in bytes */ 432 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 433 #define NAND_PAGE_SIZE_SHIFT 29 434 #define NAND_PAGE_SIZE_2K U(0) 435 #define NAND_PAGE_SIZE_4K U(1) 436 #define NAND_PAGE_SIZE_8K U(2) 437 438 /* NAND block size in pages */ 439 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 440 #define NAND_BLOCK_SIZE_SHIFT 27 441 #define NAND_BLOCK_SIZE_64_PAGES U(0) 442 #define NAND_BLOCK_SIZE_128_PAGES U(1) 443 #define NAND_BLOCK_SIZE_256_PAGES U(2) 444 445 /* NAND number of block (in unit of 256 blocs) */ 446 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 447 #define NAND_BLOCK_NB_SHIFT 19 448 #define NAND_BLOCK_NB_UNIT U(256) 449 450 /* NAND bus width in bits */ 451 #define NAND_WIDTH_MASK BIT(18) 452 #define NAND_WIDTH_SHIFT 18 453 454 /* NAND number of ECC bits per 512 bytes */ 455 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 456 #define NAND_ECC_BIT_NB_SHIFT 15 457 #define NAND_ECC_BIT_NB_UNSET U(0) 458 #define NAND_ECC_BIT_NB_1_BITS U(1) 459 #define NAND_ECC_BIT_NB_4_BITS U(2) 460 #define NAND_ECC_BIT_NB_8_BITS U(3) 461 #define NAND_ECC_ON_DIE U(4) 462 463 /* NAND number of planes */ 464 #define NAND_PLANE_BIT_NB_MASK BIT(14) 465 466 /******************************************************************************* 467 * STM32MP1 TAMP 468 ******************************************************************************/ 469 #define TAMP_BASE U(0x5C00A000) 470 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 471 472 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 473 static inline uint32_t tamp_bkpr(uint32_t idx) 474 { 475 return TAMP_BKP_REGISTER_BASE + (idx << 2); 476 } 477 #endif 478 479 /******************************************************************************* 480 * STM32MP1 DDRCTRL 481 ******************************************************************************/ 482 #define DDRCTRL_BASE U(0x5A003000) 483 484 /******************************************************************************* 485 * STM32MP1 DDRPHYC 486 ******************************************************************************/ 487 #define DDRPHYC_BASE U(0x5A004000) 488 489 /******************************************************************************* 490 * STM32MP1 IWDG 491 ******************************************************************************/ 492 #define IWDG_MAX_INSTANCE U(2) 493 #define IWDG1_INST U(0) 494 #define IWDG2_INST U(1) 495 496 #define IWDG1_BASE U(0x5C003000) 497 #define IWDG2_BASE U(0x5A002000) 498 499 /******************************************************************************* 500 * Miscellaneous STM32MP1 peripherals base address 501 ******************************************************************************/ 502 #define CRYP1_BASE U(0x54001000) 503 #define DBGMCU_BASE U(0x50081000) 504 #define HASH1_BASE U(0x54002000) 505 #define I2C4_BASE U(0x5C002000) 506 #define I2C6_BASE U(0x5c009000) 507 #define RNG1_BASE U(0x54003000) 508 #define RTC_BASE U(0x5c004000) 509 #define SPI6_BASE U(0x5c001000) 510 511 /******************************************************************************* 512 * Device Tree defines 513 ******************************************************************************/ 514 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 515 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 516 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 517 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 518 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 519 520 #endif /* STM32MP1_DEF_H */ 521