1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 14 #ifndef __ASSEMBLY__ 15 #include <boot_api.h> 16 #include <stm32mp1_dt.h> 17 #include <stm32mp1_private.h> 18 #endif 19 20 /******************************************************************************* 21 * STM32MP1 memory map related constants 22 ******************************************************************************/ 23 24 #define STM32MP1_SRAM_BASE U(0x2FFC0000) 25 #define STM32MP1_SRAM_SIZE U(0x00040000) 26 27 /* DDR configuration */ 28 #define STM32MP1_DDR_BASE U(0xC0000000) 29 #define STM32MP1_DDR_SIZE_DFLT U(0x20000000) /* 512 MB */ 30 #define STM32MP1_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 31 #define STM32MP1_DDR_SPEED_DFLT 528 32 33 /* DDR power initializations */ 34 #ifndef __ASSEMBLY__ 35 enum ddr_type { 36 STM32MP_DDR3, 37 STM32MP_LPDDR2, 38 }; 39 #endif 40 41 /* Section used inside TF binaries */ 42 #define STM32MP1_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 43 /* 256 Octets reserved for header */ 44 #define STM32MP1_HEADER_SIZE U(0x00000100) 45 46 #define STM32MP1_BINARY_BASE (STM32MP1_SRAM_BASE + \ 47 STM32MP1_PARAM_LOAD_SIZE + \ 48 STM32MP1_HEADER_SIZE) 49 50 #define STM32MP1_BINARY_SIZE (STM32MP1_SRAM_SIZE - \ 51 (STM32MP1_PARAM_LOAD_SIZE + \ 52 STM32MP1_HEADER_SIZE)) 53 54 #if STACK_PROTECTOR_ENABLED 55 #define STM32MP1_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 56 #else 57 #define STM32MP1_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 58 #endif 59 60 #define STM32MP1_BL32_BASE (STM32MP1_SRAM_BASE + \ 61 STM32MP1_SRAM_SIZE - \ 62 STM32MP1_BL32_SIZE) 63 64 #if STACK_PROTECTOR_ENABLED 65 #define STM32MP1_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 66 #else 67 #define STM32MP1_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 68 #endif 69 70 #define STM32MP1_BL2_BASE (STM32MP1_BL32_BASE - \ 71 STM32MP1_BL2_SIZE) 72 73 /* BL2 and BL32/sp_min require 5 tables */ 74 #define MAX_XLAT_TABLES 5 75 76 /* 77 * MAX_MMAP_REGIONS is usually: 78 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 79 */ 80 #if defined(IMAGE_BL2) 81 #define MAX_MMAP_REGIONS 11 82 #endif 83 #if defined(IMAGE_BL32) 84 #define MAX_MMAP_REGIONS 6 85 #endif 86 87 /* DTB initialization value */ 88 #define STM32MP1_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 89 90 #define STM32MP1_DTB_BASE (STM32MP1_BL2_BASE - \ 91 STM32MP1_DTB_SIZE) 92 93 #define STM32MP1_BL33_BASE (STM32MP1_DDR_BASE + U(0x100000)) 94 95 /******************************************************************************* 96 * STM32MP1 device/io map related constants (used for MMU) 97 ******************************************************************************/ 98 #define STM32MP1_DEVICE1_BASE U(0x40000000) 99 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 100 101 #define STM32MP1_DEVICE2_BASE U(0x80000000) 102 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 103 104 /******************************************************************************* 105 * STM32MP1 RCC 106 ******************************************************************************/ 107 #define RCC_BASE U(0x50000000) 108 109 /******************************************************************************* 110 * STM32MP1 PWR 111 ******************************************************************************/ 112 #define PWR_BASE U(0x50001000) 113 114 /******************************************************************************* 115 * STM32MP1 GPIO 116 ******************************************************************************/ 117 #define GPIOA_BASE U(0x50002000) 118 #define GPIOB_BASE U(0x50003000) 119 #define GPIOC_BASE U(0x50004000) 120 #define GPIOD_BASE U(0x50005000) 121 #define GPIOE_BASE U(0x50006000) 122 #define GPIOF_BASE U(0x50007000) 123 #define GPIOG_BASE U(0x50008000) 124 #define GPIOH_BASE U(0x50009000) 125 #define GPIOI_BASE U(0x5000A000) 126 #define GPIOJ_BASE U(0x5000B000) 127 #define GPIOK_BASE U(0x5000C000) 128 #define GPIOZ_BASE U(0x54004000) 129 #define GPIO_BANK_OFFSET U(0x1000) 130 131 /* Bank IDs used in GPIO driver API */ 132 #define GPIO_BANK_A U(0) 133 #define GPIO_BANK_B U(1) 134 #define GPIO_BANK_C U(2) 135 #define GPIO_BANK_D U(3) 136 #define GPIO_BANK_E U(4) 137 #define GPIO_BANK_F U(5) 138 #define GPIO_BANK_G U(6) 139 #define GPIO_BANK_H U(7) 140 #define GPIO_BANK_I U(8) 141 #define GPIO_BANK_J U(9) 142 #define GPIO_BANK_K U(10) 143 #define GPIO_BANK_Z U(25) 144 145 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 146 147 /******************************************************************************* 148 * STM32MP1 UART 149 ******************************************************************************/ 150 #define USART1_BASE U(0x5C000000) 151 #define USART2_BASE U(0x4000E000) 152 #define USART3_BASE U(0x4000F000) 153 #define UART4_BASE U(0x40010000) 154 #define UART5_BASE U(0x40011000) 155 #define USART6_BASE U(0x44003000) 156 #define UART7_BASE U(0x40018000) 157 #define UART8_BASE U(0x40019000) 158 #define STM32MP1_UART_BAUDRATE U(115200) 159 160 /* For UART crash console */ 161 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 162 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 163 #define STM32MP1_DEBUG_USART_CLK_FRQ 64000000 164 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 165 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 166 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 167 #define DEBUG_UART_TX_GPIO_PORT 11 168 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 169 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 170 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 171 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 172 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 173 174 /******************************************************************************* 175 * STM32MP1 TZC (TZ400) 176 ******************************************************************************/ 177 #define STM32MP1_TZC_BASE U(0x5C006000) 178 179 #define STM32MP1_TZC_A7_ID U(0) 180 #define STM32MP1_TZC_LCD_ID U(3) 181 #define STM32MP1_TZC_GPU_ID U(4) 182 #define STM32MP1_TZC_MDMA_ID U(5) 183 #define STM32MP1_TZC_DMA_ID U(6) 184 #define STM32MP1_TZC_USB_HOST_ID U(7) 185 #define STM32MP1_TZC_USB_OTG_ID U(8) 186 #define STM32MP1_TZC_SDMMC_ID U(9) 187 #define STM32MP1_TZC_ETH_ID U(10) 188 #define STM32MP1_TZC_DAP_ID U(15) 189 190 #define STM32MP1_FILTER_BIT_ALL U(3) 191 192 /******************************************************************************* 193 * STM32MP1 SDMMC 194 ******************************************************************************/ 195 #define STM32MP1_SDMMC1_BASE U(0x58005000) 196 #define STM32MP1_SDMMC2_BASE U(0x58007000) 197 #define STM32MP1_SDMMC3_BASE U(0x48004000) 198 199 #define STM32MP1_MMC_INIT_FREQ 400000 /*400 KHz*/ 200 #define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 201 #define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 202 #define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 203 #define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 204 205 /******************************************************************************* 206 * STM32MP1 BSEC / OTP 207 ******************************************************************************/ 208 #define STM32MP1_OTP_MAX_ID 0x5FU 209 #define STM32MP1_UPPER_OTP_START 0x20U 210 211 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 212 213 /* OTP offsets */ 214 #define DATA0_OTP U(0) 215 216 /* OTP mask */ 217 /* DATA0 */ 218 #define DATA0_OTP_SECURED BIT(6) 219 220 /******************************************************************************* 221 * STM32MP1 TAMP 222 ******************************************************************************/ 223 #define TAMP_BASE U(0x5C00A000) 224 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 225 226 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 227 static inline uint32_t tamp_bkpr(uint32_t idx) 228 { 229 return TAMP_BKP_REGISTER_BASE + (idx << 2); 230 } 231 #endif 232 233 /******************************************************************************* 234 * STM32MP1 DDRCTRL 235 ******************************************************************************/ 236 #define DDRCTRL_BASE U(0x5A003000) 237 238 /******************************************************************************* 239 * STM32MP1 DDRPHYC 240 ******************************************************************************/ 241 #define DDRPHYC_BASE U(0x5A004000) 242 243 /******************************************************************************* 244 * STM32MP1 I2C4 245 ******************************************************************************/ 246 #define I2C4_BASE U(0x5C002000) 247 248 #endif /* STM32MP1_DEF_H */ 249