1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #endif 29 30 /******************************************************************************* 31 * CHIP ID 32 ******************************************************************************/ 33 #define STM32MP157C_PART_NB U(0x05000000) 34 #define STM32MP157A_PART_NB U(0x05000001) 35 #define STM32MP153C_PART_NB U(0x05000024) 36 #define STM32MP153A_PART_NB U(0x05000025) 37 #define STM32MP151C_PART_NB U(0x0500002E) 38 #define STM32MP151A_PART_NB U(0x0500002F) 39 40 #define STM32MP1_REV_B U(0x2000) 41 42 /******************************************************************************* 43 * PACKAGE ID 44 ******************************************************************************/ 45 #define PKG_AA_LFBGA448 U(4) 46 #define PKG_AB_LFBGA354 U(3) 47 #define PKG_AC_TFBGA361 U(2) 48 #define PKG_AD_TFBGA257 U(1) 49 50 /******************************************************************************* 51 * STM32MP1 memory map related constants 52 ******************************************************************************/ 53 #define STM32MP_ROM_BASE U(0x00000000) 54 #define STM32MP_ROM_SIZE U(0x00020000) 55 56 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 57 #define STM32MP_SYSRAM_SIZE U(0x00040000) 58 59 /* DDR configuration */ 60 #define STM32MP_DDR_BASE U(0xC0000000) 61 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 62 #ifdef AARCH32_SP_OPTEE 63 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 64 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 65 #endif 66 67 /* DDR power initializations */ 68 #ifndef __ASSEMBLER__ 69 enum ddr_type { 70 STM32MP_DDR3, 71 STM32MP_LPDDR2, 72 STM32MP_LPDDR3 73 }; 74 #endif 75 76 /* Section used inside TF binaries */ 77 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 78 /* 256 Octets reserved for header */ 79 #define STM32MP_HEADER_SIZE U(0x00000100) 80 81 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 82 STM32MP_PARAM_LOAD_SIZE + \ 83 STM32MP_HEADER_SIZE) 84 85 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 86 (STM32MP_PARAM_LOAD_SIZE + \ 87 STM32MP_HEADER_SIZE)) 88 89 #ifdef AARCH32_SP_OPTEE 90 #define STM32MP_BL32_SIZE U(0) 91 92 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 93 94 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 95 STM32MP_OPTEE_BASE) 96 #else 97 #if STACK_PROTECTOR_ENABLED 98 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 99 #else 100 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 101 #endif 102 #endif 103 104 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 105 STM32MP_SYSRAM_SIZE - \ 106 STM32MP_BL32_SIZE) 107 108 #ifdef AARCH32_SP_OPTEE 109 #if STACK_PROTECTOR_ENABLED 110 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 111 #else 112 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 113 #endif 114 #else 115 #if STACK_PROTECTOR_ENABLED 116 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 117 #else 118 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 119 #endif 120 #endif 121 122 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 123 STM32MP_BL2_SIZE) 124 125 /* BL2 and BL32/sp_min require 4 tables */ 126 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 127 128 /* 129 * MAX_MMAP_REGIONS is usually: 130 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 131 */ 132 #if defined(IMAGE_BL2) 133 #define MAX_MMAP_REGIONS 11 134 #endif 135 #if defined(IMAGE_BL32) 136 #define MAX_MMAP_REGIONS 6 137 #endif 138 139 /* DTB initialization value */ 140 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 141 142 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 143 STM32MP_DTB_SIZE) 144 145 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 146 147 /* Define maximum page size for NAND devices */ 148 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 149 150 /******************************************************************************* 151 * STM32MP1 RAW partition offset for MTD devices 152 ******************************************************************************/ 153 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 154 #ifdef AARCH32_SP_OPTEE 155 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 156 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 157 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 158 #endif 159 160 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 161 #ifdef AARCH32_SP_OPTEE 162 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 163 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 164 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 165 #endif 166 167 /******************************************************************************* 168 * STM32MP1 device/io map related constants (used for MMU) 169 ******************************************************************************/ 170 #define STM32MP1_DEVICE1_BASE U(0x40000000) 171 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 172 173 #define STM32MP1_DEVICE2_BASE U(0x80000000) 174 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 175 176 /******************************************************************************* 177 * STM32MP1 RCC 178 ******************************************************************************/ 179 #define RCC_BASE U(0x50000000) 180 181 /******************************************************************************* 182 * STM32MP1 PWR 183 ******************************************************************************/ 184 #define PWR_BASE U(0x50001000) 185 186 /******************************************************************************* 187 * STM32MP1 GPIO 188 ******************************************************************************/ 189 #define GPIOA_BASE U(0x50002000) 190 #define GPIOB_BASE U(0x50003000) 191 #define GPIOC_BASE U(0x50004000) 192 #define GPIOD_BASE U(0x50005000) 193 #define GPIOE_BASE U(0x50006000) 194 #define GPIOF_BASE U(0x50007000) 195 #define GPIOG_BASE U(0x50008000) 196 #define GPIOH_BASE U(0x50009000) 197 #define GPIOI_BASE U(0x5000A000) 198 #define GPIOJ_BASE U(0x5000B000) 199 #define GPIOK_BASE U(0x5000C000) 200 #define GPIOZ_BASE U(0x54004000) 201 #define GPIO_BANK_OFFSET U(0x1000) 202 203 /* Bank IDs used in GPIO driver API */ 204 #define GPIO_BANK_A U(0) 205 #define GPIO_BANK_B U(1) 206 #define GPIO_BANK_C U(2) 207 #define GPIO_BANK_D U(3) 208 #define GPIO_BANK_E U(4) 209 #define GPIO_BANK_F U(5) 210 #define GPIO_BANK_G U(6) 211 #define GPIO_BANK_H U(7) 212 #define GPIO_BANK_I U(8) 213 #define GPIO_BANK_J U(9) 214 #define GPIO_BANK_K U(10) 215 #define GPIO_BANK_Z U(25) 216 217 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 218 219 /******************************************************************************* 220 * STM32MP1 UART 221 ******************************************************************************/ 222 #define USART1_BASE U(0x5C000000) 223 #define USART2_BASE U(0x4000E000) 224 #define USART3_BASE U(0x4000F000) 225 #define UART4_BASE U(0x40010000) 226 #define UART5_BASE U(0x40011000) 227 #define USART6_BASE U(0x44003000) 228 #define UART7_BASE U(0x40018000) 229 #define UART8_BASE U(0x40019000) 230 #define STM32MP_UART_BAUDRATE U(115200) 231 232 /* For UART crash console */ 233 #define STM32MP_DEBUG_USART_BASE UART4_BASE 234 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 235 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 236 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 237 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 238 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 239 #define DEBUG_UART_TX_GPIO_PORT 11 240 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 241 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 242 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 243 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 244 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 245 246 /******************************************************************************* 247 * STM32MP1 TZC (TZ400) 248 ******************************************************************************/ 249 #define STM32MP1_TZC_BASE U(0x5C006000) 250 251 #define STM32MP1_TZC_A7_ID U(0) 252 #define STM32MP1_TZC_M4_ID U(1) 253 #define STM32MP1_TZC_LCD_ID U(3) 254 #define STM32MP1_TZC_GPU_ID U(4) 255 #define STM32MP1_TZC_MDMA_ID U(5) 256 #define STM32MP1_TZC_DMA_ID U(6) 257 #define STM32MP1_TZC_USB_HOST_ID U(7) 258 #define STM32MP1_TZC_USB_OTG_ID U(8) 259 #define STM32MP1_TZC_SDMMC_ID U(9) 260 #define STM32MP1_TZC_ETH_ID U(10) 261 #define STM32MP1_TZC_DAP_ID U(15) 262 263 #define STM32MP1_FILTER_BIT_ALL U(3) 264 265 /******************************************************************************* 266 * STM32MP1 SDMMC 267 ******************************************************************************/ 268 #define STM32MP_SDMMC1_BASE U(0x58005000) 269 #define STM32MP_SDMMC2_BASE U(0x58007000) 270 #define STM32MP_SDMMC3_BASE U(0x48004000) 271 272 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 273 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 274 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 275 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 276 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 277 278 /******************************************************************************* 279 * STM32MP1 BSEC / OTP 280 ******************************************************************************/ 281 #define STM32MP1_OTP_MAX_ID 0x5FU 282 #define STM32MP1_UPPER_OTP_START 0x20U 283 284 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 285 286 /* OTP offsets */ 287 #define DATA0_OTP U(0) 288 #define PART_NUMBER_OTP U(1) 289 #define NAND_OTP U(9) 290 #define PACKAGE_OTP U(16) 291 #define HW2_OTP U(18) 292 293 /* OTP mask */ 294 /* DATA0 */ 295 #define DATA0_OTP_SECURED BIT(6) 296 297 /* PART NUMBER */ 298 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 299 #define PART_NUMBER_OTP_PART_SHIFT 0 300 301 /* PACKAGE */ 302 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 303 #define PACKAGE_OTP_PKG_SHIFT 27 304 305 /* IWDG OTP */ 306 #define HW2_OTP_IWDG_HW_POS U(3) 307 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 308 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 309 310 /* HW2 OTP */ 311 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 312 313 /* NAND OTP */ 314 /* NAND parameter storage flag */ 315 #define NAND_PARAM_STORED_IN_OTP BIT(31) 316 317 /* NAND page size in bytes */ 318 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 319 #define NAND_PAGE_SIZE_SHIFT 29 320 #define NAND_PAGE_SIZE_2K U(0) 321 #define NAND_PAGE_SIZE_4K U(1) 322 #define NAND_PAGE_SIZE_8K U(2) 323 324 /* NAND block size in pages */ 325 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 326 #define NAND_BLOCK_SIZE_SHIFT 27 327 #define NAND_BLOCK_SIZE_64_PAGES U(0) 328 #define NAND_BLOCK_SIZE_128_PAGES U(1) 329 #define NAND_BLOCK_SIZE_256_PAGES U(2) 330 331 /* NAND number of block (in unit of 256 blocs) */ 332 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 333 #define NAND_BLOCK_NB_SHIFT 19 334 #define NAND_BLOCK_NB_UNIT U(256) 335 336 /* NAND bus width in bits */ 337 #define NAND_WIDTH_MASK BIT(18) 338 #define NAND_WIDTH_SHIFT 18 339 340 /* NAND number of ECC bits per 512 bytes */ 341 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 342 #define NAND_ECC_BIT_NB_SHIFT 15 343 #define NAND_ECC_BIT_NB_UNSET U(0) 344 #define NAND_ECC_BIT_NB_1_BITS U(1) 345 #define NAND_ECC_BIT_NB_4_BITS U(2) 346 #define NAND_ECC_BIT_NB_8_BITS U(3) 347 #define NAND_ECC_ON_DIE U(4) 348 349 /* NAND number of planes */ 350 #define NAND_PLANE_BIT_NB_MASK BIT(14) 351 352 /******************************************************************************* 353 * STM32MP1 TAMP 354 ******************************************************************************/ 355 #define TAMP_BASE U(0x5C00A000) 356 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 357 358 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 359 static inline uint32_t tamp_bkpr(uint32_t idx) 360 { 361 return TAMP_BKP_REGISTER_BASE + (idx << 2); 362 } 363 #endif 364 365 /******************************************************************************* 366 * STM32MP1 DDRCTRL 367 ******************************************************************************/ 368 #define DDRCTRL_BASE U(0x5A003000) 369 370 /******************************************************************************* 371 * STM32MP1 DDRPHYC 372 ******************************************************************************/ 373 #define DDRPHYC_BASE U(0x5A004000) 374 375 /******************************************************************************* 376 * STM32MP1 IWDG 377 ******************************************************************************/ 378 #define IWDG_MAX_INSTANCE U(2) 379 #define IWDG1_INST U(0) 380 #define IWDG2_INST U(1) 381 382 #define IWDG1_BASE U(0x5C003000) 383 #define IWDG2_BASE U(0x5A002000) 384 385 /******************************************************************************* 386 * STM32MP1 I2C4 387 ******************************************************************************/ 388 #define I2C4_BASE U(0x5C002000) 389 390 /******************************************************************************* 391 * STM32MP1 DBGMCU 392 ******************************************************************************/ 393 #define DBGMCU_BASE U(0x50081000) 394 395 /******************************************************************************* 396 * Device Tree defines 397 ******************************************************************************/ 398 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 399 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 400 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 401 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 402 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 403 404 #endif /* STM32MP1_DEF_H */ 405