1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <tbbr_img_def.h> 11 #include <utils_def.h> 12 #include <xlat_tables_defs.h> 13 14 /******************************************************************************* 15 * STM32MP1 memory map related constants 16 ******************************************************************************/ 17 18 #define STM32MP1_SRAM_BASE U(0x2FFC0000) 19 #define STM32MP1_SRAM_SIZE U(0x00040000) 20 21 /* DDR configuration */ 22 #define STM32MP1_DDR_BASE U(0xC0000000) 23 #define STM32MP1_DDR_SIZE_DFLT U(0x20000000) /* 512 MB */ 24 #define STM32MP1_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 25 #define STM32MP1_DDR_SPEED_DFLT 528 26 27 /* DDR power initializations */ 28 #ifndef __ASSEMBLY__ 29 enum ddr_type { 30 STM32MP_DDR3, 31 STM32MP_LPDDR2, 32 }; 33 #endif 34 35 /* Section used inside TF binaries */ 36 #define STM32MP1_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 37 /* 256 Octets reserved for header */ 38 #define STM32MP1_HEADER_SIZE U(0x00000100) 39 40 #define STM32MP1_BINARY_BASE (STM32MP1_SRAM_BASE + \ 41 STM32MP1_PARAM_LOAD_SIZE + \ 42 STM32MP1_HEADER_SIZE) 43 44 #define STM32MP1_BINARY_SIZE (STM32MP1_SRAM_SIZE - \ 45 (STM32MP1_PARAM_LOAD_SIZE + \ 46 STM32MP1_HEADER_SIZE)) 47 48 #if STACK_PROTECTOR_ENABLED 49 #define STM32MP1_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 50 #else 51 #define STM32MP1_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 52 #endif 53 54 #define STM32MP1_BL32_BASE (STM32MP1_SRAM_BASE + \ 55 STM32MP1_SRAM_SIZE - \ 56 STM32MP1_BL32_SIZE) 57 58 #if STACK_PROTECTOR_ENABLED 59 #define STM32MP1_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 60 #else 61 #define STM32MP1_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 62 #endif 63 64 #define STM32MP1_BL2_BASE (STM32MP1_BL32_BASE - \ 65 STM32MP1_BL2_SIZE) 66 67 /* BL2 and BL32/sp_min require 5 tables */ 68 #define MAX_XLAT_TABLES 5 69 70 /* 71 * MAX_MMAP_REGIONS is usually: 72 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 73 */ 74 #if defined(IMAGE_BL2) 75 #define MAX_MMAP_REGIONS 11 76 #endif 77 #if defined(IMAGE_BL32) 78 #define MAX_MMAP_REGIONS 6 79 #endif 80 81 /* DTB initialization value */ 82 #define STM32MP1_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 83 84 #define STM32MP1_DTB_BASE (STM32MP1_BL2_BASE - \ 85 STM32MP1_DTB_SIZE) 86 87 #define STM32MP1_BL33_BASE (STM32MP1_DDR_BASE + U(0x100000)) 88 89 /******************************************************************************* 90 * STM32MP1 device/io map related constants (used for MMU) 91 ******************************************************************************/ 92 #define STM32MP1_DEVICE1_BASE U(0x40000000) 93 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 94 95 #define STM32MP1_DEVICE2_BASE U(0x80000000) 96 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 97 98 /******************************************************************************* 99 * STM32MP1 RCC 100 ******************************************************************************/ 101 #define RCC_BASE U(0x50000000) 102 103 /******************************************************************************* 104 * STM32MP1 PWR 105 ******************************************************************************/ 106 #define PWR_BASE U(0x50001000) 107 108 /******************************************************************************* 109 * STM32MP1 UART 110 ******************************************************************************/ 111 #define USART1_BASE U(0x5C000000) 112 #define USART2_BASE U(0x4000E000) 113 #define USART3_BASE U(0x4000F000) 114 #define UART4_BASE U(0x40010000) 115 #define UART5_BASE U(0x40011000) 116 #define USART6_BASE U(0x44003000) 117 #define UART7_BASE U(0x40018000) 118 #define UART8_BASE U(0x40019000) 119 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 120 #define STM32MP1_UART_BAUDRATE 115200 121 122 /******************************************************************************* 123 * STM32MP1 GIC-400 124 ******************************************************************************/ 125 #define STM32MP1_GICD_BASE U(0xA0021000) 126 #define STM32MP1_GICC_BASE U(0xA0022000) 127 #define STM32MP1_GICH_BASE U(0xA0024000) 128 #define STM32MP1_GICV_BASE U(0xA0026000) 129 130 /******************************************************************************* 131 * STM32MP1 TZC (TZ400) 132 ******************************************************************************/ 133 #define STM32MP1_TZC_BASE U(0x5C006000) 134 135 #define STM32MP1_TZC_A7_ID U(0) 136 #define STM32MP1_TZC_LCD_ID U(3) 137 #define STM32MP1_TZC_GPU_ID U(4) 138 #define STM32MP1_TZC_MDMA_ID U(5) 139 #define STM32MP1_TZC_DMA_ID U(6) 140 #define STM32MP1_TZC_USB_HOST_ID U(7) 141 #define STM32MP1_TZC_USB_OTG_ID U(8) 142 #define STM32MP1_TZC_SDMMC_ID U(9) 143 #define STM32MP1_TZC_ETH_ID U(10) 144 #define STM32MP1_TZC_DAP_ID U(15) 145 146 #define STM32MP1_MEMORY_NS 0 147 #define STM32MP1_MEMORY_SECURE 1 148 149 #define STM32MP1_FILTER_BIT_ALL 3 150 151 /******************************************************************************* 152 * STM32MP1 SDMMC 153 ******************************************************************************/ 154 #define STM32MP1_SDMMC1_BASE U(0x58005000) 155 #define STM32MP1_SDMMC2_BASE U(0x58007000) 156 #define STM32MP1_SDMMC3_BASE U(0x48004000) 157 158 #define STM32MP1_SD_INIT_FREQ 400000 /*400 KHz*/ 159 #define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 160 #define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 161 #define STM32MP1_EMMC_INIT_FREQ STM32MP1_SD_INIT_FREQ 162 #define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 163 #define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 164 165 /******************************************************************************* 166 * STM32MP1 TAMP 167 ******************************************************************************/ 168 #define TAMP_BASE U(0x5C00A000) 169 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 170 171 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 172 static inline uint32_t tamp_bkpr(uint32_t idx) 173 { 174 return TAMP_BKP_REGISTER_BASE + (idx << 2); 175 } 176 #endif 177 178 /******************************************************************************* 179 * STM32MP1 DDRCTRL 180 ******************************************************************************/ 181 #define DDRCTRL_BASE U(0x5A003000) 182 183 /******************************************************************************* 184 * STM32MP1 DDRPHYC 185 ******************************************************************************/ 186 #define DDRPHYC_BASE U(0x5A004000) 187 188 /******************************************************************************* 189 * STM32MP1 I2C4 190 ******************************************************************************/ 191 #define I2C4_BASE U(0x5C002000) 192 193 #endif /* STM32MP1_DEF_H */ 194