1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #include <stm32mp1_shared_resources.h> 28 #endif 29 30 #if !STM32MP_USE_STM32IMAGE 31 #include "stm32mp1_fip_def.h" 32 #else /* STM32MP_USE_STM32IMAGE */ 33 #include "stm32mp1_stm32image_def.h" 34 #endif /* STM32MP_USE_STM32IMAGE */ 35 36 /******************************************************************************* 37 * CHIP ID 38 ******************************************************************************/ 39 #if STM32MP13 40 #define STM32MP1_CHIP_ID U(0x501) 41 42 #define STM32MP135C_PART_NB U(0x05010000) 43 #define STM32MP135A_PART_NB U(0x05010001) 44 #define STM32MP133C_PART_NB U(0x050100C0) 45 #define STM32MP133A_PART_NB U(0x050100C1) 46 #define STM32MP131C_PART_NB U(0x050106C8) 47 #define STM32MP131A_PART_NB U(0x050106C9) 48 #define STM32MP135F_PART_NB U(0x05010800) 49 #define STM32MP135D_PART_NB U(0x05010801) 50 #define STM32MP133F_PART_NB U(0x050108C0) 51 #define STM32MP133D_PART_NB U(0x050108C1) 52 #define STM32MP131F_PART_NB U(0x05010EC8) 53 #define STM32MP131D_PART_NB U(0x05010EC9) 54 #endif 55 #if STM32MP15 56 #define STM32MP1_CHIP_ID U(0x500) 57 58 #define STM32MP157C_PART_NB U(0x05000000) 59 #define STM32MP157A_PART_NB U(0x05000001) 60 #define STM32MP153C_PART_NB U(0x05000024) 61 #define STM32MP153A_PART_NB U(0x05000025) 62 #define STM32MP151C_PART_NB U(0x0500002E) 63 #define STM32MP151A_PART_NB U(0x0500002F) 64 #define STM32MP157F_PART_NB U(0x05000080) 65 #define STM32MP157D_PART_NB U(0x05000081) 66 #define STM32MP153F_PART_NB U(0x050000A4) 67 #define STM32MP153D_PART_NB U(0x050000A5) 68 #define STM32MP151F_PART_NB U(0x050000AE) 69 #define STM32MP151D_PART_NB U(0x050000AF) 70 #endif 71 72 #define STM32MP1_REV_B U(0x2000) 73 #if STM32MP13 74 #define STM32MP1_REV_Z U(0x1001) 75 #endif 76 #if STM32MP15 77 #define STM32MP1_REV_Z U(0x2001) 78 #endif 79 80 /******************************************************************************* 81 * PACKAGE ID 82 ******************************************************************************/ 83 #if STM32MP15 84 #define PKG_AA_LFBGA448 U(4) 85 #define PKG_AB_LFBGA354 U(3) 86 #define PKG_AC_TFBGA361 U(2) 87 #define PKG_AD_TFBGA257 U(1) 88 #endif 89 90 /******************************************************************************* 91 * STM32MP1 memory map related constants 92 ******************************************************************************/ 93 #define STM32MP_ROM_BASE U(0x00000000) 94 #define STM32MP_ROM_SIZE U(0x00020000) 95 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 96 97 #if STM32MP13 98 #define STM32MP_SYSRAM_BASE U(0x2FFE0000) 99 #define STM32MP_SYSRAM_SIZE U(0x00020000) 100 #define SRAM1_BASE U(0x30000000) 101 #define SRAM1_SIZE U(0x00004000) 102 #define SRAM2_BASE U(0x30004000) 103 #define SRAM2_SIZE U(0x00002000) 104 #define SRAM3_BASE U(0x30006000) 105 #define SRAM3_SIZE U(0x00002000) 106 #endif /* STM32MP13 */ 107 #if STM32MP15 108 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 109 #define STM32MP_SYSRAM_SIZE U(0x00040000) 110 #endif /* STM32MP15 */ 111 112 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 113 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 114 STM32MP_SYSRAM_SIZE - \ 115 STM32MP_NS_SYSRAM_SIZE) 116 117 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 118 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 119 120 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 121 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 122 STM32MP_NS_SYSRAM_SIZE) 123 124 /* DDR configuration */ 125 #define STM32MP_DDR_BASE U(0xC0000000) 126 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 127 128 /* DDR power initializations */ 129 #ifndef __ASSEMBLER__ 130 enum ddr_type { 131 STM32MP_DDR3, 132 STM32MP_LPDDR2, 133 STM32MP_LPDDR3 134 }; 135 #endif 136 137 /* Section used inside TF binaries */ 138 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 139 /* 256 Octets reserved for header */ 140 #define STM32MP_HEADER_SIZE U(0x00000100) 141 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 142 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 143 144 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 145 STM32MP_PARAM_LOAD_SIZE + \ 146 STM32MP_HEADER_SIZE) 147 148 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 149 (STM32MP_PARAM_LOAD_SIZE + \ 150 STM32MP_HEADER_SIZE)) 151 152 /* BL2 and BL32/sp_min require finer granularity tables */ 153 #if defined(IMAGE_BL2) 154 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 155 #endif 156 157 #if defined(IMAGE_BL32) 158 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 159 #endif 160 161 /* 162 * MAX_MMAP_REGIONS is usually: 163 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 164 */ 165 #if defined(IMAGE_BL2) 166 #if STM32MP_USB_PROGRAMMER 167 #define MAX_MMAP_REGIONS 8 168 #else 169 #define MAX_MMAP_REGIONS 7 170 #endif 171 #endif 172 173 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 174 #define STM32MP_BL33_MAX_SIZE U(0x400000) 175 176 /* Define maximum page size for NAND devices */ 177 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 178 179 /******************************************************************************* 180 * STM32MP1 device/io map related constants (used for MMU) 181 ******************************************************************************/ 182 #define STM32MP1_DEVICE1_BASE U(0x40000000) 183 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 184 185 #define STM32MP1_DEVICE2_BASE U(0x80000000) 186 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 187 188 /******************************************************************************* 189 * STM32MP1 RCC 190 ******************************************************************************/ 191 #define RCC_BASE U(0x50000000) 192 193 /******************************************************************************* 194 * STM32MP1 PWR 195 ******************************************************************************/ 196 #define PWR_BASE U(0x50001000) 197 198 /******************************************************************************* 199 * STM32MP1 GPIO 200 ******************************************************************************/ 201 #define GPIOA_BASE U(0x50002000) 202 #define GPIOB_BASE U(0x50003000) 203 #define GPIOC_BASE U(0x50004000) 204 #define GPIOD_BASE U(0x50005000) 205 #define GPIOE_BASE U(0x50006000) 206 #define GPIOF_BASE U(0x50007000) 207 #define GPIOG_BASE U(0x50008000) 208 #define GPIOH_BASE U(0x50009000) 209 #define GPIOI_BASE U(0x5000A000) 210 #if STM32MP15 211 #define GPIOJ_BASE U(0x5000B000) 212 #define GPIOK_BASE U(0x5000C000) 213 #define GPIOZ_BASE U(0x54004000) 214 #endif 215 #define GPIO_BANK_OFFSET U(0x1000) 216 217 /* Bank IDs used in GPIO driver API */ 218 #define GPIO_BANK_A U(0) 219 #define GPIO_BANK_B U(1) 220 #define GPIO_BANK_C U(2) 221 #define GPIO_BANK_D U(3) 222 #define GPIO_BANK_E U(4) 223 #define GPIO_BANK_F U(5) 224 #define GPIO_BANK_G U(6) 225 #define GPIO_BANK_H U(7) 226 #define GPIO_BANK_I U(8) 227 #if STM32MP15 228 #define GPIO_BANK_J U(9) 229 #define GPIO_BANK_K U(10) 230 #define GPIO_BANK_Z U(25) 231 232 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 233 #endif 234 235 /******************************************************************************* 236 * STM32MP1 UART 237 ******************************************************************************/ 238 #define USART1_BASE U(0x5C000000) 239 #define USART2_BASE U(0x4000E000) 240 #define USART3_BASE U(0x4000F000) 241 #define UART4_BASE U(0x40010000) 242 #define UART5_BASE U(0x40011000) 243 #define USART6_BASE U(0x44003000) 244 #define UART7_BASE U(0x40018000) 245 #define UART8_BASE U(0x40019000) 246 247 /* For UART crash console */ 248 #define STM32MP_DEBUG_USART_BASE UART4_BASE 249 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 250 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 251 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 252 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 253 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 254 #define DEBUG_UART_TX_GPIO_PORT 11 255 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 256 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 257 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 258 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 259 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 260 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 261 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 262 263 /******************************************************************************* 264 * STM32MP1 ETZPC 265 ******************************************************************************/ 266 #define STM32MP1_ETZPC_BASE U(0x5C007000) 267 268 /* ETZPC TZMA IDs */ 269 #define STM32MP1_ETZPC_TZMA_ROM U(0) 270 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 271 272 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 273 274 /* ETZPC DECPROT IDs */ 275 #define STM32MP1_ETZPC_STGENC_ID 0 276 #define STM32MP1_ETZPC_BKPSRAM_ID 1 277 #define STM32MP1_ETZPC_IWDG1_ID 2 278 #define STM32MP1_ETZPC_USART1_ID 3 279 #define STM32MP1_ETZPC_SPI6_ID 4 280 #define STM32MP1_ETZPC_I2C4_ID 5 281 #define STM32MP1_ETZPC_RNG1_ID 7 282 #define STM32MP1_ETZPC_HASH1_ID 8 283 #define STM32MP1_ETZPC_CRYP1_ID 9 284 #define STM32MP1_ETZPC_DDRCTRL_ID 10 285 #define STM32MP1_ETZPC_DDRPHYC_ID 11 286 #define STM32MP1_ETZPC_I2C6_ID 12 287 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 288 289 #define STM32MP1_ETZPC_TIM2_ID 16 290 #define STM32MP1_ETZPC_TIM3_ID 17 291 #define STM32MP1_ETZPC_TIM4_ID 18 292 #define STM32MP1_ETZPC_TIM5_ID 19 293 #define STM32MP1_ETZPC_TIM6_ID 20 294 #define STM32MP1_ETZPC_TIM7_ID 21 295 #define STM32MP1_ETZPC_TIM12_ID 22 296 #define STM32MP1_ETZPC_TIM13_ID 23 297 #define STM32MP1_ETZPC_TIM14_ID 24 298 #define STM32MP1_ETZPC_LPTIM1_ID 25 299 #define STM32MP1_ETZPC_WWDG1_ID 26 300 #define STM32MP1_ETZPC_SPI2_ID 27 301 #define STM32MP1_ETZPC_SPI3_ID 28 302 #define STM32MP1_ETZPC_SPDIFRX_ID 29 303 #define STM32MP1_ETZPC_USART2_ID 30 304 #define STM32MP1_ETZPC_USART3_ID 31 305 #define STM32MP1_ETZPC_UART4_ID 32 306 #define STM32MP1_ETZPC_UART5_ID 33 307 #define STM32MP1_ETZPC_I2C1_ID 34 308 #define STM32MP1_ETZPC_I2C2_ID 35 309 #define STM32MP1_ETZPC_I2C3_ID 36 310 #define STM32MP1_ETZPC_I2C5_ID 37 311 #define STM32MP1_ETZPC_CEC_ID 38 312 #define STM32MP1_ETZPC_DAC_ID 39 313 #define STM32MP1_ETZPC_UART7_ID 40 314 #define STM32MP1_ETZPC_UART8_ID 41 315 #define STM32MP1_ETZPC_MDIOS_ID 44 316 #define STM32MP1_ETZPC_TIM1_ID 48 317 #define STM32MP1_ETZPC_TIM8_ID 49 318 #define STM32MP1_ETZPC_USART6_ID 51 319 #define STM32MP1_ETZPC_SPI1_ID 52 320 #define STM32MP1_ETZPC_SPI4_ID 53 321 #define STM32MP1_ETZPC_TIM15_ID 54 322 #define STM32MP1_ETZPC_TIM16_ID 55 323 #define STM32MP1_ETZPC_TIM17_ID 56 324 #define STM32MP1_ETZPC_SPI5_ID 57 325 #define STM32MP1_ETZPC_SAI1_ID 58 326 #define STM32MP1_ETZPC_SAI2_ID 59 327 #define STM32MP1_ETZPC_SAI3_ID 60 328 #define STM32MP1_ETZPC_DFSDM_ID 61 329 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 330 #define STM32MP1_ETZPC_LPTIM2_ID 64 331 #define STM32MP1_ETZPC_LPTIM3_ID 65 332 #define STM32MP1_ETZPC_LPTIM4_ID 66 333 #define STM32MP1_ETZPC_LPTIM5_ID 67 334 #define STM32MP1_ETZPC_SAI4_ID 68 335 #define STM32MP1_ETZPC_VREFBUF_ID 69 336 #define STM32MP1_ETZPC_DCMI_ID 70 337 #define STM32MP1_ETZPC_CRC2_ID 71 338 #define STM32MP1_ETZPC_ADC_ID 72 339 #define STM32MP1_ETZPC_HASH2_ID 73 340 #define STM32MP1_ETZPC_RNG2_ID 74 341 #define STM32MP1_ETZPC_CRYP2_ID 75 342 #define STM32MP1_ETZPC_SRAM1_ID 80 343 #define STM32MP1_ETZPC_SRAM2_ID 81 344 #define STM32MP1_ETZPC_SRAM3_ID 82 345 #define STM32MP1_ETZPC_SRAM4_ID 83 346 #define STM32MP1_ETZPC_RETRAM_ID 84 347 #define STM32MP1_ETZPC_OTG_ID 85 348 #define STM32MP1_ETZPC_SDMMC3_ID 86 349 #define STM32MP1_ETZPC_DLYBSD3_ID 87 350 #define STM32MP1_ETZPC_DMA1_ID 88 351 #define STM32MP1_ETZPC_DMA2_ID 89 352 #define STM32MP1_ETZPC_DMAMUX_ID 90 353 #define STM32MP1_ETZPC_FMC_ID 91 354 #define STM32MP1_ETZPC_QSPI_ID 92 355 #define STM32MP1_ETZPC_DLYBQ_ID 93 356 #define STM32MP1_ETZPC_ETH_ID 94 357 #define STM32MP1_ETZPC_RSV_ID 95 358 359 #define STM32MP_ETZPC_MAX_ID 96 360 361 /******************************************************************************* 362 * STM32MP1 TZC (TZ400) 363 ******************************************************************************/ 364 #define STM32MP1_TZC_BASE U(0x5C006000) 365 366 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 367 TZC_400_REGION_ATTR_FILTER_BIT(1)) 368 369 /******************************************************************************* 370 * STM32MP1 SDMMC 371 ******************************************************************************/ 372 #define STM32MP_SDMMC1_BASE U(0x58005000) 373 #define STM32MP_SDMMC2_BASE U(0x58007000) 374 #define STM32MP_SDMMC3_BASE U(0x48004000) 375 376 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 377 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 378 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 379 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 380 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 381 382 /******************************************************************************* 383 * STM32MP1 BSEC / OTP 384 ******************************************************************************/ 385 #define STM32MP1_OTP_MAX_ID 0x5FU 386 #define STM32MP1_UPPER_OTP_START 0x20U 387 388 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 389 390 /* OTP labels */ 391 #define CFG0_OTP "cfg0_otp" 392 #define PART_NUMBER_OTP "part_number_otp" 393 #if STM32MP15 394 #define PACKAGE_OTP "package_otp" 395 #endif 396 #define HW2_OTP "hw2_otp" 397 #define NAND_OTP "nand_otp" 398 #define MONOTONIC_OTP "monotonic_otp" 399 #define UID_OTP "uid_otp" 400 #define BOARD_ID_OTP "board_id" 401 402 /* OTP mask */ 403 /* CFG0 */ 404 #define CFG0_CLOSED_DEVICE BIT(6) 405 406 /* PART NUMBER */ 407 #if STM32MP13 408 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0) 409 #endif 410 #if STM32MP15 411 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 412 #endif 413 #define PART_NUMBER_OTP_PART_SHIFT 0 414 415 /* PACKAGE */ 416 #if STM32MP15 417 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 418 #define PACKAGE_OTP_PKG_SHIFT 27 419 #endif 420 421 /* IWDG OTP */ 422 #define HW2_OTP_IWDG_HW_POS U(3) 423 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 424 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 425 426 /* HW2 OTP */ 427 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 428 429 /* NAND OTP */ 430 /* NAND parameter storage flag */ 431 #define NAND_PARAM_STORED_IN_OTP BIT(31) 432 433 /* NAND page size in bytes */ 434 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 435 #define NAND_PAGE_SIZE_SHIFT 29 436 #define NAND_PAGE_SIZE_2K U(0) 437 #define NAND_PAGE_SIZE_4K U(1) 438 #define NAND_PAGE_SIZE_8K U(2) 439 440 /* NAND block size in pages */ 441 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 442 #define NAND_BLOCK_SIZE_SHIFT 27 443 #define NAND_BLOCK_SIZE_64_PAGES U(0) 444 #define NAND_BLOCK_SIZE_128_PAGES U(1) 445 #define NAND_BLOCK_SIZE_256_PAGES U(2) 446 447 /* NAND number of block (in unit of 256 blocs) */ 448 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 449 #define NAND_BLOCK_NB_SHIFT 19 450 #define NAND_BLOCK_NB_UNIT U(256) 451 452 /* NAND bus width in bits */ 453 #define NAND_WIDTH_MASK BIT(18) 454 #define NAND_WIDTH_SHIFT 18 455 456 /* NAND number of ECC bits per 512 bytes */ 457 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 458 #define NAND_ECC_BIT_NB_SHIFT 15 459 #define NAND_ECC_BIT_NB_UNSET U(0) 460 #define NAND_ECC_BIT_NB_1_BITS U(1) 461 #define NAND_ECC_BIT_NB_4_BITS U(2) 462 #define NAND_ECC_BIT_NB_8_BITS U(3) 463 #define NAND_ECC_ON_DIE U(4) 464 465 /* NAND number of planes */ 466 #define NAND_PLANE_BIT_NB_MASK BIT(14) 467 468 /* MONOTONIC OTP */ 469 #define MAX_MONOTONIC_VALUE 32 470 471 /* UID OTP */ 472 #define UID_WORD_NB U(3) 473 474 /******************************************************************************* 475 * STM32MP1 TAMP 476 ******************************************************************************/ 477 #define TAMP_BASE U(0x5C00A000) 478 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 479 480 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 481 static inline uintptr_t tamp_bkpr(uint32_t idx) 482 { 483 return TAMP_BKP_REGISTER_BASE + (idx << 2); 484 } 485 #endif 486 487 /******************************************************************************* 488 * STM32MP1 USB 489 ******************************************************************************/ 490 #define USB_OTG_BASE U(0x49000000) 491 492 /******************************************************************************* 493 * STM32MP1 DDRCTRL 494 ******************************************************************************/ 495 #define DDRCTRL_BASE U(0x5A003000) 496 497 /******************************************************************************* 498 * STM32MP1 DDRPHYC 499 ******************************************************************************/ 500 #define DDRPHYC_BASE U(0x5A004000) 501 502 /******************************************************************************* 503 * STM32MP1 IWDG 504 ******************************************************************************/ 505 #define IWDG_MAX_INSTANCE U(2) 506 #define IWDG1_INST U(0) 507 #define IWDG2_INST U(1) 508 509 #define IWDG1_BASE U(0x5C003000) 510 #define IWDG2_BASE U(0x5A002000) 511 512 /******************************************************************************* 513 * Miscellaneous STM32MP1 peripherals base address 514 ******************************************************************************/ 515 #define BSEC_BASE U(0x5C005000) 516 #if STM32MP13 517 #define CRYP_BASE U(0x54002000) 518 #endif 519 #if STM32MP15 520 #define CRYP1_BASE U(0x54001000) 521 #endif 522 #define DBGMCU_BASE U(0x50081000) 523 #if STM32MP13 524 #define HASH_BASE U(0x54003000) 525 #endif 526 #if STM32MP15 527 #define HASH1_BASE U(0x54002000) 528 #endif 529 #if STM32MP13 530 #define I2C3_BASE U(0x4C004000) 531 #define I2C4_BASE U(0x4C005000) 532 #define I2C5_BASE U(0x4C006000) 533 #endif 534 #if STM32MP15 535 #define I2C4_BASE U(0x5C002000) 536 #define I2C6_BASE U(0x5c009000) 537 #endif 538 #if STM32MP13 539 #define RNG_BASE U(0x54004000) 540 #endif 541 #if STM32MP15 542 #define RNG1_BASE U(0x54003000) 543 #endif 544 #define RTC_BASE U(0x5c004000) 545 #if STM32MP13 546 #define SPI4_BASE U(0x4C002000) 547 #define SPI5_BASE U(0x4C003000) 548 #endif 549 #if STM32MP15 550 #define SPI6_BASE U(0x5c001000) 551 #endif 552 #define STGEN_BASE U(0x5c008000) 553 #define SYSCFG_BASE U(0x50020000) 554 555 /******************************************************************************* 556 * STM32MP13 SAES 557 ******************************************************************************/ 558 #define SAES_BASE U(0x54005000) 559 560 /******************************************************************************* 561 * STM32MP13 PKA 562 ******************************************************************************/ 563 #define PKA_BASE U(0x54006000) 564 565 /******************************************************************************* 566 * REGULATORS 567 ******************************************************************************/ 568 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 569 #define PLAT_NB_RDEVS U(19) 570 /* 1 FIXED */ 571 #define PLAT_NB_FIXED_REGS U(1) 572 573 /******************************************************************************* 574 * Device Tree defines 575 ******************************************************************************/ 576 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 577 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 578 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 579 #define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout" 580 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 581 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 582 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 583 584 #endif /* STM32MP1_DEF_H */ 585