1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #include <stm32mp1_shared_resources.h> 29 #endif 30 31 /******************************************************************************* 32 * CHIP ID 33 ******************************************************************************/ 34 #define STM32MP157C_PART_NB U(0x05000000) 35 #define STM32MP157A_PART_NB U(0x05000001) 36 #define STM32MP153C_PART_NB U(0x05000024) 37 #define STM32MP153A_PART_NB U(0x05000025) 38 #define STM32MP151C_PART_NB U(0x0500002E) 39 #define STM32MP151A_PART_NB U(0x0500002F) 40 #define STM32MP157F_PART_NB U(0x05000080) 41 #define STM32MP157D_PART_NB U(0x05000081) 42 #define STM32MP153F_PART_NB U(0x050000A4) 43 #define STM32MP153D_PART_NB U(0x050000A5) 44 #define STM32MP151F_PART_NB U(0x050000AE) 45 #define STM32MP151D_PART_NB U(0x050000AF) 46 47 #define STM32MP1_REV_B U(0x2000) 48 #define STM32MP1_REV_Z U(0x2001) 49 50 /******************************************************************************* 51 * PACKAGE ID 52 ******************************************************************************/ 53 #define PKG_AA_LFBGA448 U(4) 54 #define PKG_AB_LFBGA354 U(3) 55 #define PKG_AC_TFBGA361 U(2) 56 #define PKG_AD_TFBGA257 U(1) 57 58 /******************************************************************************* 59 * STM32MP1 memory map related constants 60 ******************************************************************************/ 61 #define STM32MP_ROM_BASE U(0x00000000) 62 #define STM32MP_ROM_SIZE U(0x00020000) 63 64 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 65 #define STM32MP_SYSRAM_SIZE U(0x00040000) 66 67 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 68 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 69 STM32MP_SYSRAM_SIZE - \ 70 STM32MP_NS_SYSRAM_SIZE) 71 72 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 73 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 74 75 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 76 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 77 STM32MP_NS_SYSRAM_SIZE) 78 79 /* DDR configuration */ 80 #define STM32MP_DDR_BASE U(0xC0000000) 81 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 82 #ifdef AARCH32_SP_OPTEE 83 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 84 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 85 #else 86 #define STM32MP_DDR_S_SIZE U(0) 87 #define STM32MP_DDR_SHMEM_SIZE U(0) 88 #endif 89 90 /* DDR power initializations */ 91 #ifndef __ASSEMBLER__ 92 enum ddr_type { 93 STM32MP_DDR3, 94 STM32MP_LPDDR2, 95 STM32MP_LPDDR3 96 }; 97 #endif 98 99 /* Section used inside TF binaries */ 100 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 101 /* 256 Octets reserved for header */ 102 #define STM32MP_HEADER_SIZE U(0x00000100) 103 104 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 105 STM32MP_PARAM_LOAD_SIZE + \ 106 STM32MP_HEADER_SIZE) 107 108 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 109 (STM32MP_PARAM_LOAD_SIZE + \ 110 STM32MP_HEADER_SIZE)) 111 112 #ifdef AARCH32_SP_OPTEE 113 #define STM32MP_BL32_SIZE U(0) 114 115 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 116 117 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 118 STM32MP_OPTEE_BASE) 119 #else 120 #if STACK_PROTECTOR_ENABLED 121 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 122 #else 123 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 124 #endif 125 #endif 126 127 #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ 128 STM32MP_SEC_SYSRAM_SIZE - \ 129 STM32MP_BL32_SIZE) 130 131 #ifdef AARCH32_SP_OPTEE 132 #if STACK_PROTECTOR_ENABLED 133 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 134 #else 135 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 136 #endif 137 #else 138 #if STACK_PROTECTOR_ENABLED 139 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 140 #else 141 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 142 #endif 143 #endif 144 145 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 146 STM32MP_BL2_SIZE) 147 148 /* BL2 and BL32/sp_min require 4 tables */ 149 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 150 151 /* 152 * MAX_MMAP_REGIONS is usually: 153 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 154 */ 155 #if defined(IMAGE_BL2) 156 #define MAX_MMAP_REGIONS 11 157 #endif 158 #if defined(IMAGE_BL32) 159 #define MAX_MMAP_REGIONS 6 160 #endif 161 162 /* DTB initialization value */ 163 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 164 165 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 166 STM32MP_DTB_SIZE) 167 168 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 169 170 /* Define maximum page size for NAND devices */ 171 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 172 173 /******************************************************************************* 174 * STM32MP1 RAW partition offset for MTD devices 175 ******************************************************************************/ 176 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 177 #ifdef AARCH32_SP_OPTEE 178 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 179 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 180 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 181 #endif 182 183 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 184 #ifdef AARCH32_SP_OPTEE 185 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 186 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 187 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 188 #endif 189 190 /******************************************************************************* 191 * STM32MP1 device/io map related constants (used for MMU) 192 ******************************************************************************/ 193 #define STM32MP1_DEVICE1_BASE U(0x40000000) 194 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 195 196 #define STM32MP1_DEVICE2_BASE U(0x80000000) 197 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 198 199 /******************************************************************************* 200 * STM32MP1 RCC 201 ******************************************************************************/ 202 #define RCC_BASE U(0x50000000) 203 204 /******************************************************************************* 205 * STM32MP1 PWR 206 ******************************************************************************/ 207 #define PWR_BASE U(0x50001000) 208 209 /******************************************************************************* 210 * STM32MP1 GPIO 211 ******************************************************************************/ 212 #define GPIOA_BASE U(0x50002000) 213 #define GPIOB_BASE U(0x50003000) 214 #define GPIOC_BASE U(0x50004000) 215 #define GPIOD_BASE U(0x50005000) 216 #define GPIOE_BASE U(0x50006000) 217 #define GPIOF_BASE U(0x50007000) 218 #define GPIOG_BASE U(0x50008000) 219 #define GPIOH_BASE U(0x50009000) 220 #define GPIOI_BASE U(0x5000A000) 221 #define GPIOJ_BASE U(0x5000B000) 222 #define GPIOK_BASE U(0x5000C000) 223 #define GPIOZ_BASE U(0x54004000) 224 #define GPIO_BANK_OFFSET U(0x1000) 225 226 /* Bank IDs used in GPIO driver API */ 227 #define GPIO_BANK_A U(0) 228 #define GPIO_BANK_B U(1) 229 #define GPIO_BANK_C U(2) 230 #define GPIO_BANK_D U(3) 231 #define GPIO_BANK_E U(4) 232 #define GPIO_BANK_F U(5) 233 #define GPIO_BANK_G U(6) 234 #define GPIO_BANK_H U(7) 235 #define GPIO_BANK_I U(8) 236 #define GPIO_BANK_J U(9) 237 #define GPIO_BANK_K U(10) 238 #define GPIO_BANK_Z U(25) 239 240 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 241 242 /******************************************************************************* 243 * STM32MP1 UART 244 ******************************************************************************/ 245 #define USART1_BASE U(0x5C000000) 246 #define USART2_BASE U(0x4000E000) 247 #define USART3_BASE U(0x4000F000) 248 #define UART4_BASE U(0x40010000) 249 #define UART5_BASE U(0x40011000) 250 #define USART6_BASE U(0x44003000) 251 #define UART7_BASE U(0x40018000) 252 #define UART8_BASE U(0x40019000) 253 #define STM32MP_UART_BAUDRATE U(115200) 254 255 /* For UART crash console */ 256 #define STM32MP_DEBUG_USART_BASE UART4_BASE 257 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 258 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 259 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 260 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 261 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 262 #define DEBUG_UART_TX_GPIO_PORT 11 263 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 264 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 265 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 266 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 267 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 268 269 /******************************************************************************* 270 * STM32MP1 ETZPC 271 ******************************************************************************/ 272 #define STM32MP1_ETZPC_BASE U(0x5C007000) 273 274 /* ETZPC TZMA IDs */ 275 #define STM32MP1_ETZPC_TZMA_ROM U(0) 276 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 277 278 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 279 280 /* ETZPC DECPROT IDs */ 281 #define STM32MP1_ETZPC_STGENC_ID 0 282 #define STM32MP1_ETZPC_BKPSRAM_ID 1 283 #define STM32MP1_ETZPC_IWDG1_ID 2 284 #define STM32MP1_ETZPC_USART1_ID 3 285 #define STM32MP1_ETZPC_SPI6_ID 4 286 #define STM32MP1_ETZPC_I2C4_ID 5 287 #define STM32MP1_ETZPC_RNG1_ID 7 288 #define STM32MP1_ETZPC_HASH1_ID 8 289 #define STM32MP1_ETZPC_CRYP1_ID 9 290 #define STM32MP1_ETZPC_DDRCTRL_ID 10 291 #define STM32MP1_ETZPC_DDRPHYC_ID 11 292 #define STM32MP1_ETZPC_I2C6_ID 12 293 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 294 295 #define STM32MP1_ETZPC_TIM2_ID 16 296 #define STM32MP1_ETZPC_TIM3_ID 17 297 #define STM32MP1_ETZPC_TIM4_ID 18 298 #define STM32MP1_ETZPC_TIM5_ID 19 299 #define STM32MP1_ETZPC_TIM6_ID 20 300 #define STM32MP1_ETZPC_TIM7_ID 21 301 #define STM32MP1_ETZPC_TIM12_ID 22 302 #define STM32MP1_ETZPC_TIM13_ID 23 303 #define STM32MP1_ETZPC_TIM14_ID 24 304 #define STM32MP1_ETZPC_LPTIM1_ID 25 305 #define STM32MP1_ETZPC_WWDG1_ID 26 306 #define STM32MP1_ETZPC_SPI2_ID 27 307 #define STM32MP1_ETZPC_SPI3_ID 28 308 #define STM32MP1_ETZPC_SPDIFRX_ID 29 309 #define STM32MP1_ETZPC_USART2_ID 30 310 #define STM32MP1_ETZPC_USART3_ID 31 311 #define STM32MP1_ETZPC_UART4_ID 32 312 #define STM32MP1_ETZPC_UART5_ID 33 313 #define STM32MP1_ETZPC_I2C1_ID 34 314 #define STM32MP1_ETZPC_I2C2_ID 35 315 #define STM32MP1_ETZPC_I2C3_ID 36 316 #define STM32MP1_ETZPC_I2C5_ID 37 317 #define STM32MP1_ETZPC_CEC_ID 38 318 #define STM32MP1_ETZPC_DAC_ID 39 319 #define STM32MP1_ETZPC_UART7_ID 40 320 #define STM32MP1_ETZPC_UART8_ID 41 321 #define STM32MP1_ETZPC_MDIOS_ID 44 322 #define STM32MP1_ETZPC_TIM1_ID 48 323 #define STM32MP1_ETZPC_TIM8_ID 49 324 #define STM32MP1_ETZPC_USART6_ID 51 325 #define STM32MP1_ETZPC_SPI1_ID 52 326 #define STM32MP1_ETZPC_SPI4_ID 53 327 #define STM32MP1_ETZPC_TIM15_ID 54 328 #define STM32MP1_ETZPC_TIM16_ID 55 329 #define STM32MP1_ETZPC_TIM17_ID 56 330 #define STM32MP1_ETZPC_SPI5_ID 57 331 #define STM32MP1_ETZPC_SAI1_ID 58 332 #define STM32MP1_ETZPC_SAI2_ID 59 333 #define STM32MP1_ETZPC_SAI3_ID 60 334 #define STM32MP1_ETZPC_DFSDM_ID 61 335 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 336 #define STM32MP1_ETZPC_LPTIM2_ID 64 337 #define STM32MP1_ETZPC_LPTIM3_ID 65 338 #define STM32MP1_ETZPC_LPTIM4_ID 66 339 #define STM32MP1_ETZPC_LPTIM5_ID 67 340 #define STM32MP1_ETZPC_SAI4_ID 68 341 #define STM32MP1_ETZPC_VREFBUF_ID 69 342 #define STM32MP1_ETZPC_DCMI_ID 70 343 #define STM32MP1_ETZPC_CRC2_ID 71 344 #define STM32MP1_ETZPC_ADC_ID 72 345 #define STM32MP1_ETZPC_HASH2_ID 73 346 #define STM32MP1_ETZPC_RNG2_ID 74 347 #define STM32MP1_ETZPC_CRYP2_ID 75 348 #define STM32MP1_ETZPC_SRAM1_ID 80 349 #define STM32MP1_ETZPC_SRAM2_ID 81 350 #define STM32MP1_ETZPC_SRAM3_ID 82 351 #define STM32MP1_ETZPC_SRAM4_ID 83 352 #define STM32MP1_ETZPC_RETRAM_ID 84 353 #define STM32MP1_ETZPC_OTG_ID 85 354 #define STM32MP1_ETZPC_SDMMC3_ID 86 355 #define STM32MP1_ETZPC_DLYBSD3_ID 87 356 #define STM32MP1_ETZPC_DMA1_ID 88 357 #define STM32MP1_ETZPC_DMA2_ID 89 358 #define STM32MP1_ETZPC_DMAMUX_ID 90 359 #define STM32MP1_ETZPC_FMC_ID 91 360 #define STM32MP1_ETZPC_QSPI_ID 92 361 #define STM32MP1_ETZPC_DLYBQ_ID 93 362 #define STM32MP1_ETZPC_ETH_ID 94 363 #define STM32MP1_ETZPC_RSV_ID 95 364 365 #define STM32MP_ETZPC_MAX_ID 96 366 367 /******************************************************************************* 368 * STM32MP1 TZC (TZ400) 369 ******************************************************************************/ 370 #define STM32MP1_TZC_BASE U(0x5C006000) 371 372 #define STM32MP1_TZC_A7_ID U(0) 373 #define STM32MP1_TZC_M4_ID U(1) 374 #define STM32MP1_TZC_LCD_ID U(3) 375 #define STM32MP1_TZC_GPU_ID U(4) 376 #define STM32MP1_TZC_MDMA_ID U(5) 377 #define STM32MP1_TZC_DMA_ID U(6) 378 #define STM32MP1_TZC_USB_HOST_ID U(7) 379 #define STM32MP1_TZC_USB_OTG_ID U(8) 380 #define STM32MP1_TZC_SDMMC_ID U(9) 381 #define STM32MP1_TZC_ETH_ID U(10) 382 #define STM32MP1_TZC_DAP_ID U(15) 383 384 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 385 TZC_400_REGION_ATTR_FILTER_BIT(1)) 386 387 /******************************************************************************* 388 * STM32MP1 SDMMC 389 ******************************************************************************/ 390 #define STM32MP_SDMMC1_BASE U(0x58005000) 391 #define STM32MP_SDMMC2_BASE U(0x58007000) 392 #define STM32MP_SDMMC3_BASE U(0x48004000) 393 394 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 395 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 396 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 397 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 398 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 399 400 /******************************************************************************* 401 * STM32MP1 BSEC / OTP 402 ******************************************************************************/ 403 #define STM32MP1_OTP_MAX_ID 0x5FU 404 #define STM32MP1_UPPER_OTP_START 0x20U 405 406 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 407 408 /* OTP offsets */ 409 #define DATA0_OTP U(0) 410 #define PART_NUMBER_OTP U(1) 411 #define NAND_OTP U(9) 412 #define PACKAGE_OTP U(16) 413 #define HW2_OTP U(18) 414 415 /* OTP mask */ 416 /* DATA0 */ 417 #define DATA0_OTP_SECURED BIT(6) 418 419 /* PART NUMBER */ 420 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 421 #define PART_NUMBER_OTP_PART_SHIFT 0 422 423 /* PACKAGE */ 424 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 425 #define PACKAGE_OTP_PKG_SHIFT 27 426 427 /* IWDG OTP */ 428 #define HW2_OTP_IWDG_HW_POS U(3) 429 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 430 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 431 432 /* HW2 OTP */ 433 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 434 435 /* NAND OTP */ 436 /* NAND parameter storage flag */ 437 #define NAND_PARAM_STORED_IN_OTP BIT(31) 438 439 /* NAND page size in bytes */ 440 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 441 #define NAND_PAGE_SIZE_SHIFT 29 442 #define NAND_PAGE_SIZE_2K U(0) 443 #define NAND_PAGE_SIZE_4K U(1) 444 #define NAND_PAGE_SIZE_8K U(2) 445 446 /* NAND block size in pages */ 447 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 448 #define NAND_BLOCK_SIZE_SHIFT 27 449 #define NAND_BLOCK_SIZE_64_PAGES U(0) 450 #define NAND_BLOCK_SIZE_128_PAGES U(1) 451 #define NAND_BLOCK_SIZE_256_PAGES U(2) 452 453 /* NAND number of block (in unit of 256 blocs) */ 454 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 455 #define NAND_BLOCK_NB_SHIFT 19 456 #define NAND_BLOCK_NB_UNIT U(256) 457 458 /* NAND bus width in bits */ 459 #define NAND_WIDTH_MASK BIT(18) 460 #define NAND_WIDTH_SHIFT 18 461 462 /* NAND number of ECC bits per 512 bytes */ 463 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 464 #define NAND_ECC_BIT_NB_SHIFT 15 465 #define NAND_ECC_BIT_NB_UNSET U(0) 466 #define NAND_ECC_BIT_NB_1_BITS U(1) 467 #define NAND_ECC_BIT_NB_4_BITS U(2) 468 #define NAND_ECC_BIT_NB_8_BITS U(3) 469 #define NAND_ECC_ON_DIE U(4) 470 471 /* NAND number of planes */ 472 #define NAND_PLANE_BIT_NB_MASK BIT(14) 473 474 /******************************************************************************* 475 * STM32MP1 TAMP 476 ******************************************************************************/ 477 #define TAMP_BASE U(0x5C00A000) 478 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 479 480 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 481 static inline uint32_t tamp_bkpr(uint32_t idx) 482 { 483 return TAMP_BKP_REGISTER_BASE + (idx << 2); 484 } 485 #endif 486 487 /******************************************************************************* 488 * STM32MP1 DDRCTRL 489 ******************************************************************************/ 490 #define DDRCTRL_BASE U(0x5A003000) 491 492 /******************************************************************************* 493 * STM32MP1 DDRPHYC 494 ******************************************************************************/ 495 #define DDRPHYC_BASE U(0x5A004000) 496 497 /******************************************************************************* 498 * STM32MP1 IWDG 499 ******************************************************************************/ 500 #define IWDG_MAX_INSTANCE U(2) 501 #define IWDG1_INST U(0) 502 #define IWDG2_INST U(1) 503 504 #define IWDG1_BASE U(0x5C003000) 505 #define IWDG2_BASE U(0x5A002000) 506 507 /******************************************************************************* 508 * Miscellaneous STM32MP1 peripherals base address 509 ******************************************************************************/ 510 #define BSEC_BASE U(0x5C005000) 511 #define CRYP1_BASE U(0x54001000) 512 #define DBGMCU_BASE U(0x50081000) 513 #define HASH1_BASE U(0x54002000) 514 #define I2C4_BASE U(0x5C002000) 515 #define I2C6_BASE U(0x5c009000) 516 #define RNG1_BASE U(0x54003000) 517 #define RTC_BASE U(0x5c004000) 518 #define SPI6_BASE U(0x5c001000) 519 #define STGEN_BASE U(0x5c008000) 520 #define SYSCFG_BASE U(0x50020000) 521 522 /******************************************************************************* 523 * Device Tree defines 524 ******************************************************************************/ 525 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 526 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 527 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 528 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 529 530 #endif /* STM32MP1_DEF_H */ 531