1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_common.h> 23 #include <stm32mp_dt.h> 24 #include <stm32mp_shres_helpers.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #endif 28 29 /******************************************************************************* 30 * CHIP ID 31 ******************************************************************************/ 32 #define STM32MP157C_PART_NB U(0x05000000) 33 #define STM32MP157A_PART_NB U(0x05000001) 34 #define STM32MP153C_PART_NB U(0x05000024) 35 #define STM32MP153A_PART_NB U(0x05000025) 36 #define STM32MP151C_PART_NB U(0x0500002E) 37 #define STM32MP151A_PART_NB U(0x0500002F) 38 39 #define STM32MP1_REV_B U(0x2000) 40 41 /******************************************************************************* 42 * PACKAGE ID 43 ******************************************************************************/ 44 #define PKG_AA_LFBGA448 U(4) 45 #define PKG_AB_LFBGA354 U(3) 46 #define PKG_AC_TFBGA361 U(2) 47 #define PKG_AD_TFBGA257 U(1) 48 49 /******************************************************************************* 50 * STM32MP1 memory map related constants 51 ******************************************************************************/ 52 53 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 54 #define STM32MP_SYSRAM_SIZE U(0x00040000) 55 56 /* DDR configuration */ 57 #define STM32MP_DDR_BASE U(0xC0000000) 58 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 59 #ifdef AARCH32_SP_OPTEE 60 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 61 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 62 #endif 63 64 /* DDR power initializations */ 65 #ifndef __ASSEMBLER__ 66 enum ddr_type { 67 STM32MP_DDR3, 68 STM32MP_LPDDR2, 69 STM32MP_LPDDR3 70 }; 71 #endif 72 73 /* Section used inside TF binaries */ 74 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 75 /* 256 Octets reserved for header */ 76 #define STM32MP_HEADER_SIZE U(0x00000100) 77 78 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 79 STM32MP_PARAM_LOAD_SIZE + \ 80 STM32MP_HEADER_SIZE) 81 82 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 83 (STM32MP_PARAM_LOAD_SIZE + \ 84 STM32MP_HEADER_SIZE)) 85 86 #ifdef AARCH32_SP_OPTEE 87 #define STM32MP_BL32_SIZE U(0) 88 89 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 90 91 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 92 STM32MP_OPTEE_BASE) 93 #else 94 #if STACK_PROTECTOR_ENABLED 95 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 96 #else 97 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 98 #endif 99 #endif 100 101 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 102 STM32MP_SYSRAM_SIZE - \ 103 STM32MP_BL32_SIZE) 104 105 #ifdef AARCH32_SP_OPTEE 106 #if STACK_PROTECTOR_ENABLED 107 #define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ 108 #else 109 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ 110 #endif 111 #else 112 #if STACK_PROTECTOR_ENABLED 113 #define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ 114 #else 115 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ 116 #endif 117 #endif 118 119 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 120 STM32MP_BL2_SIZE) 121 122 /* BL2 and BL32/sp_min require 5 tables */ 123 #define MAX_XLAT_TABLES 5 124 125 /* 126 * MAX_MMAP_REGIONS is usually: 127 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 128 */ 129 #if defined(IMAGE_BL2) 130 #define MAX_MMAP_REGIONS 11 131 #endif 132 #if defined(IMAGE_BL32) 133 #define MAX_MMAP_REGIONS 6 134 #endif 135 136 /* DTB initialization value */ 137 #define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */ 138 139 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 140 STM32MP_DTB_SIZE) 141 142 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 143 144 /******************************************************************************* 145 * STM32MP1 device/io map related constants (used for MMU) 146 ******************************************************************************/ 147 #define STM32MP1_DEVICE1_BASE U(0x40000000) 148 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 149 150 #define STM32MP1_DEVICE2_BASE U(0x80000000) 151 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 152 153 /******************************************************************************* 154 * STM32MP1 RCC 155 ******************************************************************************/ 156 #define RCC_BASE U(0x50000000) 157 158 /******************************************************************************* 159 * STM32MP1 PWR 160 ******************************************************************************/ 161 #define PWR_BASE U(0x50001000) 162 163 /******************************************************************************* 164 * STM32MP1 GPIO 165 ******************************************************************************/ 166 #define GPIOA_BASE U(0x50002000) 167 #define GPIOB_BASE U(0x50003000) 168 #define GPIOC_BASE U(0x50004000) 169 #define GPIOD_BASE U(0x50005000) 170 #define GPIOE_BASE U(0x50006000) 171 #define GPIOF_BASE U(0x50007000) 172 #define GPIOG_BASE U(0x50008000) 173 #define GPIOH_BASE U(0x50009000) 174 #define GPIOI_BASE U(0x5000A000) 175 #define GPIOJ_BASE U(0x5000B000) 176 #define GPIOK_BASE U(0x5000C000) 177 #define GPIOZ_BASE U(0x54004000) 178 #define GPIO_BANK_OFFSET U(0x1000) 179 180 /* Bank IDs used in GPIO driver API */ 181 #define GPIO_BANK_A U(0) 182 #define GPIO_BANK_B U(1) 183 #define GPIO_BANK_C U(2) 184 #define GPIO_BANK_D U(3) 185 #define GPIO_BANK_E U(4) 186 #define GPIO_BANK_F U(5) 187 #define GPIO_BANK_G U(6) 188 #define GPIO_BANK_H U(7) 189 #define GPIO_BANK_I U(8) 190 #define GPIO_BANK_J U(9) 191 #define GPIO_BANK_K U(10) 192 #define GPIO_BANK_Z U(25) 193 194 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 195 196 /******************************************************************************* 197 * STM32MP1 UART 198 ******************************************************************************/ 199 #define USART1_BASE U(0x5C000000) 200 #define USART2_BASE U(0x4000E000) 201 #define USART3_BASE U(0x4000F000) 202 #define UART4_BASE U(0x40010000) 203 #define UART5_BASE U(0x40011000) 204 #define USART6_BASE U(0x44003000) 205 #define UART7_BASE U(0x40018000) 206 #define UART8_BASE U(0x40019000) 207 #define STM32MP_UART_BAUDRATE U(115200) 208 209 /* For UART crash console */ 210 #define STM32MP_DEBUG_USART_BASE UART4_BASE 211 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 212 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 213 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 214 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 215 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 216 #define DEBUG_UART_TX_GPIO_PORT 11 217 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 218 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 219 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 220 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 221 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 222 223 /******************************************************************************* 224 * STM32MP1 TZC (TZ400) 225 ******************************************************************************/ 226 #define STM32MP1_TZC_BASE U(0x5C006000) 227 228 #define STM32MP1_TZC_A7_ID U(0) 229 #define STM32MP1_TZC_M4_ID U(1) 230 #define STM32MP1_TZC_LCD_ID U(3) 231 #define STM32MP1_TZC_GPU_ID U(4) 232 #define STM32MP1_TZC_MDMA_ID U(5) 233 #define STM32MP1_TZC_DMA_ID U(6) 234 #define STM32MP1_TZC_USB_HOST_ID U(7) 235 #define STM32MP1_TZC_USB_OTG_ID U(8) 236 #define STM32MP1_TZC_SDMMC_ID U(9) 237 #define STM32MP1_TZC_ETH_ID U(10) 238 #define STM32MP1_TZC_DAP_ID U(15) 239 240 #define STM32MP1_FILTER_BIT_ALL U(3) 241 242 /******************************************************************************* 243 * STM32MP1 SDMMC 244 ******************************************************************************/ 245 #define STM32MP_SDMMC1_BASE U(0x58005000) 246 #define STM32MP_SDMMC2_BASE U(0x58007000) 247 #define STM32MP_SDMMC3_BASE U(0x48004000) 248 249 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 250 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 251 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 252 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 253 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 254 255 /******************************************************************************* 256 * STM32MP1 BSEC / OTP 257 ******************************************************************************/ 258 #define STM32MP1_OTP_MAX_ID 0x5FU 259 #define STM32MP1_UPPER_OTP_START 0x20U 260 261 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 262 263 /* OTP offsets */ 264 #define DATA0_OTP U(0) 265 #define PART_NUMBER_OTP U(1) 266 #define PACKAGE_OTP U(16) 267 #define HW2_OTP U(18) 268 269 /* OTP mask */ 270 /* DATA0 */ 271 #define DATA0_OTP_SECURED BIT(6) 272 273 /* PART NUMBER */ 274 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 275 #define PART_NUMBER_OTP_PART_SHIFT 0 276 277 /* PACKAGE */ 278 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 279 #define PACKAGE_OTP_PKG_SHIFT 27 280 281 /* IWDG OTP */ 282 #define HW2_OTP_IWDG_HW_POS U(3) 283 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 284 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 285 286 /* HW2 OTP */ 287 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 288 289 /******************************************************************************* 290 * STM32MP1 TAMP 291 ******************************************************************************/ 292 #define TAMP_BASE U(0x5C00A000) 293 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 294 295 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 296 static inline uint32_t tamp_bkpr(uint32_t idx) 297 { 298 return TAMP_BKP_REGISTER_BASE + (idx << 2); 299 } 300 #endif 301 302 /******************************************************************************* 303 * STM32MP1 DDRCTRL 304 ******************************************************************************/ 305 #define DDRCTRL_BASE U(0x5A003000) 306 307 /******************************************************************************* 308 * STM32MP1 DDRPHYC 309 ******************************************************************************/ 310 #define DDRPHYC_BASE U(0x5A004000) 311 312 /******************************************************************************* 313 * STM32MP1 IWDG 314 ******************************************************************************/ 315 #define IWDG_MAX_INSTANCE U(2) 316 #define IWDG1_INST U(0) 317 #define IWDG2_INST U(1) 318 319 #define IWDG1_BASE U(0x5C003000) 320 #define IWDG2_BASE U(0x5A002000) 321 322 /******************************************************************************* 323 * STM32MP1 I2C4 324 ******************************************************************************/ 325 #define I2C4_BASE U(0x5C002000) 326 327 /******************************************************************************* 328 * STM32MP1 DBGMCU 329 ******************************************************************************/ 330 #define DBGMCU_BASE U(0x50081000) 331 332 /******************************************************************************* 333 * Device Tree defines 334 ******************************************************************************/ 335 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 336 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 337 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 338 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 339 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 340 341 #endif /* STM32MP1_DEF_H */ 342