1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #include <stm32mp1_shared_resources.h> 28 #endif 29 30 #if !STM32MP_USE_STM32IMAGE 31 #include "stm32mp1_fip_def.h" 32 #else /* STM32MP_USE_STM32IMAGE */ 33 #include "stm32mp1_stm32image_def.h" 34 #endif /* STM32MP_USE_STM32IMAGE */ 35 36 /******************************************************************************* 37 * CHIP ID 38 ******************************************************************************/ 39 #define STM32MP1_CHIP_ID U(0x500) 40 41 #define STM32MP157C_PART_NB U(0x05000000) 42 #define STM32MP157A_PART_NB U(0x05000001) 43 #define STM32MP153C_PART_NB U(0x05000024) 44 #define STM32MP153A_PART_NB U(0x05000025) 45 #define STM32MP151C_PART_NB U(0x0500002E) 46 #define STM32MP151A_PART_NB U(0x0500002F) 47 #define STM32MP157F_PART_NB U(0x05000080) 48 #define STM32MP157D_PART_NB U(0x05000081) 49 #define STM32MP153F_PART_NB U(0x050000A4) 50 #define STM32MP153D_PART_NB U(0x050000A5) 51 #define STM32MP151F_PART_NB U(0x050000AE) 52 #define STM32MP151D_PART_NB U(0x050000AF) 53 54 #define STM32MP1_REV_B U(0x2000) 55 #define STM32MP1_REV_Z U(0x2001) 56 57 /******************************************************************************* 58 * PACKAGE ID 59 ******************************************************************************/ 60 #define PKG_AA_LFBGA448 U(4) 61 #define PKG_AB_LFBGA354 U(3) 62 #define PKG_AC_TFBGA361 U(2) 63 #define PKG_AD_TFBGA257 U(1) 64 65 /******************************************************************************* 66 * STM32MP1 memory map related constants 67 ******************************************************************************/ 68 #define STM32MP_ROM_BASE U(0x00000000) 69 #define STM32MP_ROM_SIZE U(0x00020000) 70 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 71 72 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 75 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 76 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 77 STM32MP_SYSRAM_SIZE - \ 78 STM32MP_NS_SYSRAM_SIZE) 79 80 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 81 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 82 83 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 84 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 85 STM32MP_NS_SYSRAM_SIZE) 86 87 /* DDR configuration */ 88 #define STM32MP_DDR_BASE U(0xC0000000) 89 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 90 91 /* DDR power initializations */ 92 #ifndef __ASSEMBLER__ 93 enum ddr_type { 94 STM32MP_DDR3, 95 STM32MP_LPDDR2, 96 STM32MP_LPDDR3 97 }; 98 #endif 99 100 /* Section used inside TF binaries */ 101 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 102 /* 256 Octets reserved for header */ 103 #define STM32MP_HEADER_SIZE U(0x00000100) 104 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 105 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 106 107 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 108 STM32MP_PARAM_LOAD_SIZE + \ 109 STM32MP_HEADER_SIZE) 110 111 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 112 (STM32MP_PARAM_LOAD_SIZE + \ 113 STM32MP_HEADER_SIZE)) 114 115 /* BL2 and BL32/sp_min require finer granularity tables */ 116 #if defined(IMAGE_BL2) 117 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 118 #endif 119 120 #if defined(IMAGE_BL32) 121 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 122 #endif 123 124 /* 125 * MAX_MMAP_REGIONS is usually: 126 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 127 */ 128 #if defined(IMAGE_BL2) 129 #if STM32MP_USB_PROGRAMMER 130 #define MAX_MMAP_REGIONS 8 131 #else 132 #define MAX_MMAP_REGIONS 7 133 #endif 134 #endif 135 136 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 137 #define STM32MP_BL33_MAX_SIZE U(0x400000) 138 139 /* Define maximum page size for NAND devices */ 140 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 141 142 /******************************************************************************* 143 * STM32MP1 device/io map related constants (used for MMU) 144 ******************************************************************************/ 145 #define STM32MP1_DEVICE1_BASE U(0x40000000) 146 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 147 148 #define STM32MP1_DEVICE2_BASE U(0x80000000) 149 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 150 151 /******************************************************************************* 152 * STM32MP1 RCC 153 ******************************************************************************/ 154 #define RCC_BASE U(0x50000000) 155 156 /******************************************************************************* 157 * STM32MP1 PWR 158 ******************************************************************************/ 159 #define PWR_BASE U(0x50001000) 160 161 /******************************************************************************* 162 * STM32MP1 GPIO 163 ******************************************************************************/ 164 #define GPIOA_BASE U(0x50002000) 165 #define GPIOB_BASE U(0x50003000) 166 #define GPIOC_BASE U(0x50004000) 167 #define GPIOD_BASE U(0x50005000) 168 #define GPIOE_BASE U(0x50006000) 169 #define GPIOF_BASE U(0x50007000) 170 #define GPIOG_BASE U(0x50008000) 171 #define GPIOH_BASE U(0x50009000) 172 #define GPIOI_BASE U(0x5000A000) 173 #define GPIOJ_BASE U(0x5000B000) 174 #define GPIOK_BASE U(0x5000C000) 175 #define GPIOZ_BASE U(0x54004000) 176 #define GPIO_BANK_OFFSET U(0x1000) 177 178 /* Bank IDs used in GPIO driver API */ 179 #define GPIO_BANK_A U(0) 180 #define GPIO_BANK_B U(1) 181 #define GPIO_BANK_C U(2) 182 #define GPIO_BANK_D U(3) 183 #define GPIO_BANK_E U(4) 184 #define GPIO_BANK_F U(5) 185 #define GPIO_BANK_G U(6) 186 #define GPIO_BANK_H U(7) 187 #define GPIO_BANK_I U(8) 188 #define GPIO_BANK_J U(9) 189 #define GPIO_BANK_K U(10) 190 #define GPIO_BANK_Z U(25) 191 192 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 193 194 /******************************************************************************* 195 * STM32MP1 UART 196 ******************************************************************************/ 197 #define USART1_BASE U(0x5C000000) 198 #define USART2_BASE U(0x4000E000) 199 #define USART3_BASE U(0x4000F000) 200 #define UART4_BASE U(0x40010000) 201 #define UART5_BASE U(0x40011000) 202 #define USART6_BASE U(0x44003000) 203 #define UART7_BASE U(0x40018000) 204 #define UART8_BASE U(0x40019000) 205 206 /* For UART crash console */ 207 #define STM32MP_DEBUG_USART_BASE UART4_BASE 208 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 209 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 210 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 211 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 212 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 213 #define DEBUG_UART_TX_GPIO_PORT 11 214 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 215 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 216 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 217 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 218 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 219 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 220 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 221 222 /******************************************************************************* 223 * STM32MP1 ETZPC 224 ******************************************************************************/ 225 #define STM32MP1_ETZPC_BASE U(0x5C007000) 226 227 /* ETZPC TZMA IDs */ 228 #define STM32MP1_ETZPC_TZMA_ROM U(0) 229 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 230 231 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 232 233 /* ETZPC DECPROT IDs */ 234 #define STM32MP1_ETZPC_STGENC_ID 0 235 #define STM32MP1_ETZPC_BKPSRAM_ID 1 236 #define STM32MP1_ETZPC_IWDG1_ID 2 237 #define STM32MP1_ETZPC_USART1_ID 3 238 #define STM32MP1_ETZPC_SPI6_ID 4 239 #define STM32MP1_ETZPC_I2C4_ID 5 240 #define STM32MP1_ETZPC_RNG1_ID 7 241 #define STM32MP1_ETZPC_HASH1_ID 8 242 #define STM32MP1_ETZPC_CRYP1_ID 9 243 #define STM32MP1_ETZPC_DDRCTRL_ID 10 244 #define STM32MP1_ETZPC_DDRPHYC_ID 11 245 #define STM32MP1_ETZPC_I2C6_ID 12 246 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 247 248 #define STM32MP1_ETZPC_TIM2_ID 16 249 #define STM32MP1_ETZPC_TIM3_ID 17 250 #define STM32MP1_ETZPC_TIM4_ID 18 251 #define STM32MP1_ETZPC_TIM5_ID 19 252 #define STM32MP1_ETZPC_TIM6_ID 20 253 #define STM32MP1_ETZPC_TIM7_ID 21 254 #define STM32MP1_ETZPC_TIM12_ID 22 255 #define STM32MP1_ETZPC_TIM13_ID 23 256 #define STM32MP1_ETZPC_TIM14_ID 24 257 #define STM32MP1_ETZPC_LPTIM1_ID 25 258 #define STM32MP1_ETZPC_WWDG1_ID 26 259 #define STM32MP1_ETZPC_SPI2_ID 27 260 #define STM32MP1_ETZPC_SPI3_ID 28 261 #define STM32MP1_ETZPC_SPDIFRX_ID 29 262 #define STM32MP1_ETZPC_USART2_ID 30 263 #define STM32MP1_ETZPC_USART3_ID 31 264 #define STM32MP1_ETZPC_UART4_ID 32 265 #define STM32MP1_ETZPC_UART5_ID 33 266 #define STM32MP1_ETZPC_I2C1_ID 34 267 #define STM32MP1_ETZPC_I2C2_ID 35 268 #define STM32MP1_ETZPC_I2C3_ID 36 269 #define STM32MP1_ETZPC_I2C5_ID 37 270 #define STM32MP1_ETZPC_CEC_ID 38 271 #define STM32MP1_ETZPC_DAC_ID 39 272 #define STM32MP1_ETZPC_UART7_ID 40 273 #define STM32MP1_ETZPC_UART8_ID 41 274 #define STM32MP1_ETZPC_MDIOS_ID 44 275 #define STM32MP1_ETZPC_TIM1_ID 48 276 #define STM32MP1_ETZPC_TIM8_ID 49 277 #define STM32MP1_ETZPC_USART6_ID 51 278 #define STM32MP1_ETZPC_SPI1_ID 52 279 #define STM32MP1_ETZPC_SPI4_ID 53 280 #define STM32MP1_ETZPC_TIM15_ID 54 281 #define STM32MP1_ETZPC_TIM16_ID 55 282 #define STM32MP1_ETZPC_TIM17_ID 56 283 #define STM32MP1_ETZPC_SPI5_ID 57 284 #define STM32MP1_ETZPC_SAI1_ID 58 285 #define STM32MP1_ETZPC_SAI2_ID 59 286 #define STM32MP1_ETZPC_SAI3_ID 60 287 #define STM32MP1_ETZPC_DFSDM_ID 61 288 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 289 #define STM32MP1_ETZPC_LPTIM2_ID 64 290 #define STM32MP1_ETZPC_LPTIM3_ID 65 291 #define STM32MP1_ETZPC_LPTIM4_ID 66 292 #define STM32MP1_ETZPC_LPTIM5_ID 67 293 #define STM32MP1_ETZPC_SAI4_ID 68 294 #define STM32MP1_ETZPC_VREFBUF_ID 69 295 #define STM32MP1_ETZPC_DCMI_ID 70 296 #define STM32MP1_ETZPC_CRC2_ID 71 297 #define STM32MP1_ETZPC_ADC_ID 72 298 #define STM32MP1_ETZPC_HASH2_ID 73 299 #define STM32MP1_ETZPC_RNG2_ID 74 300 #define STM32MP1_ETZPC_CRYP2_ID 75 301 #define STM32MP1_ETZPC_SRAM1_ID 80 302 #define STM32MP1_ETZPC_SRAM2_ID 81 303 #define STM32MP1_ETZPC_SRAM3_ID 82 304 #define STM32MP1_ETZPC_SRAM4_ID 83 305 #define STM32MP1_ETZPC_RETRAM_ID 84 306 #define STM32MP1_ETZPC_OTG_ID 85 307 #define STM32MP1_ETZPC_SDMMC3_ID 86 308 #define STM32MP1_ETZPC_DLYBSD3_ID 87 309 #define STM32MP1_ETZPC_DMA1_ID 88 310 #define STM32MP1_ETZPC_DMA2_ID 89 311 #define STM32MP1_ETZPC_DMAMUX_ID 90 312 #define STM32MP1_ETZPC_FMC_ID 91 313 #define STM32MP1_ETZPC_QSPI_ID 92 314 #define STM32MP1_ETZPC_DLYBQ_ID 93 315 #define STM32MP1_ETZPC_ETH_ID 94 316 #define STM32MP1_ETZPC_RSV_ID 95 317 318 #define STM32MP_ETZPC_MAX_ID 96 319 320 /******************************************************************************* 321 * STM32MP1 TZC (TZ400) 322 ******************************************************************************/ 323 #define STM32MP1_TZC_BASE U(0x5C006000) 324 325 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 326 TZC_400_REGION_ATTR_FILTER_BIT(1)) 327 328 /******************************************************************************* 329 * STM32MP1 SDMMC 330 ******************************************************************************/ 331 #define STM32MP_SDMMC1_BASE U(0x58005000) 332 #define STM32MP_SDMMC2_BASE U(0x58007000) 333 #define STM32MP_SDMMC3_BASE U(0x48004000) 334 335 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 336 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 337 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 338 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 339 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 340 341 /******************************************************************************* 342 * STM32MP1 BSEC / OTP 343 ******************************************************************************/ 344 #define STM32MP1_OTP_MAX_ID 0x5FU 345 #define STM32MP1_UPPER_OTP_START 0x20U 346 347 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 348 349 /* OTP labels */ 350 #define CFG0_OTP "cfg0_otp" 351 #define PART_NUMBER_OTP "part_number_otp" 352 #define PACKAGE_OTP "package_otp" 353 #define HW2_OTP "hw2_otp" 354 #define NAND_OTP "nand_otp" 355 #define MONOTONIC_OTP "monotonic_otp" 356 #define UID_OTP "uid_otp" 357 #define BOARD_ID_OTP "board_id" 358 359 /* OTP mask */ 360 /* CFG0 */ 361 #define CFG0_CLOSED_DEVICE BIT(6) 362 363 /* PART NUMBER */ 364 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 365 #define PART_NUMBER_OTP_PART_SHIFT 0 366 367 /* PACKAGE */ 368 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 369 #define PACKAGE_OTP_PKG_SHIFT 27 370 371 /* IWDG OTP */ 372 #define HW2_OTP_IWDG_HW_POS U(3) 373 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 374 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 375 376 /* HW2 OTP */ 377 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 378 379 /* NAND OTP */ 380 /* NAND parameter storage flag */ 381 #define NAND_PARAM_STORED_IN_OTP BIT(31) 382 383 /* NAND page size in bytes */ 384 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 385 #define NAND_PAGE_SIZE_SHIFT 29 386 #define NAND_PAGE_SIZE_2K U(0) 387 #define NAND_PAGE_SIZE_4K U(1) 388 #define NAND_PAGE_SIZE_8K U(2) 389 390 /* NAND block size in pages */ 391 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 392 #define NAND_BLOCK_SIZE_SHIFT 27 393 #define NAND_BLOCK_SIZE_64_PAGES U(0) 394 #define NAND_BLOCK_SIZE_128_PAGES U(1) 395 #define NAND_BLOCK_SIZE_256_PAGES U(2) 396 397 /* NAND number of block (in unit of 256 blocs) */ 398 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 399 #define NAND_BLOCK_NB_SHIFT 19 400 #define NAND_BLOCK_NB_UNIT U(256) 401 402 /* NAND bus width in bits */ 403 #define NAND_WIDTH_MASK BIT(18) 404 #define NAND_WIDTH_SHIFT 18 405 406 /* NAND number of ECC bits per 512 bytes */ 407 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 408 #define NAND_ECC_BIT_NB_SHIFT 15 409 #define NAND_ECC_BIT_NB_UNSET U(0) 410 #define NAND_ECC_BIT_NB_1_BITS U(1) 411 #define NAND_ECC_BIT_NB_4_BITS U(2) 412 #define NAND_ECC_BIT_NB_8_BITS U(3) 413 #define NAND_ECC_ON_DIE U(4) 414 415 /* NAND number of planes */ 416 #define NAND_PLANE_BIT_NB_MASK BIT(14) 417 418 /* MONOTONIC OTP */ 419 #define MAX_MONOTONIC_VALUE 32 420 421 /* UID OTP */ 422 #define UID_WORD_NB U(3) 423 424 /******************************************************************************* 425 * STM32MP1 TAMP 426 ******************************************************************************/ 427 #define TAMP_BASE U(0x5C00A000) 428 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 429 430 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 431 static inline uintptr_t tamp_bkpr(uint32_t idx) 432 { 433 return TAMP_BKP_REGISTER_BASE + (idx << 2); 434 } 435 #endif 436 437 /******************************************************************************* 438 * STM32MP1 USB 439 ******************************************************************************/ 440 #define USB_OTG_BASE U(0x49000000) 441 442 /******************************************************************************* 443 * STM32MP1 DDRCTRL 444 ******************************************************************************/ 445 #define DDRCTRL_BASE U(0x5A003000) 446 447 /******************************************************************************* 448 * STM32MP1 DDRPHYC 449 ******************************************************************************/ 450 #define DDRPHYC_BASE U(0x5A004000) 451 452 /******************************************************************************* 453 * STM32MP1 IWDG 454 ******************************************************************************/ 455 #define IWDG_MAX_INSTANCE U(2) 456 #define IWDG1_INST U(0) 457 #define IWDG2_INST U(1) 458 459 #define IWDG1_BASE U(0x5C003000) 460 #define IWDG2_BASE U(0x5A002000) 461 462 /******************************************************************************* 463 * Miscellaneous STM32MP1 peripherals base address 464 ******************************************************************************/ 465 #define BSEC_BASE U(0x5C005000) 466 #define CRYP1_BASE U(0x54001000) 467 #define DBGMCU_BASE U(0x50081000) 468 #define HASH1_BASE U(0x54002000) 469 #define I2C4_BASE U(0x5C002000) 470 #define I2C6_BASE U(0x5c009000) 471 #define RNG1_BASE U(0x54003000) 472 #define RTC_BASE U(0x5c004000) 473 #define SPI6_BASE U(0x5c001000) 474 #define STGEN_BASE U(0x5c008000) 475 #define SYSCFG_BASE U(0x50020000) 476 477 /******************************************************************************* 478 * REGULATORS 479 ******************************************************************************/ 480 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 481 #define PLAT_NB_RDEVS U(19) 482 /* 1 FIXED */ 483 #define PLAT_NB_FIXED_REGS U(1) 484 485 /******************************************************************************* 486 * Device Tree defines 487 ******************************************************************************/ 488 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 489 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 490 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 491 #define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout" 492 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 493 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 494 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 495 496 #endif /* STM32MP1_DEF_H */ 497