1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #include <stm32mp1_shared_resources.h> 29 #endif 30 31 #if !STM32MP_USE_STM32IMAGE 32 #include "stm32mp1_fip_def.h" 33 #else /* STM32MP_USE_STM32IMAGE */ 34 #include "stm32mp1_stm32image_def.h" 35 #endif /* STM32MP_USE_STM32IMAGE */ 36 37 /******************************************************************************* 38 * CHIP ID 39 ******************************************************************************/ 40 #define STM32MP1_CHIP_ID U(0x500) 41 42 #define STM32MP157C_PART_NB U(0x05000000) 43 #define STM32MP157A_PART_NB U(0x05000001) 44 #define STM32MP153C_PART_NB U(0x05000024) 45 #define STM32MP153A_PART_NB U(0x05000025) 46 #define STM32MP151C_PART_NB U(0x0500002E) 47 #define STM32MP151A_PART_NB U(0x0500002F) 48 #define STM32MP157F_PART_NB U(0x05000080) 49 #define STM32MP157D_PART_NB U(0x05000081) 50 #define STM32MP153F_PART_NB U(0x050000A4) 51 #define STM32MP153D_PART_NB U(0x050000A5) 52 #define STM32MP151F_PART_NB U(0x050000AE) 53 #define STM32MP151D_PART_NB U(0x050000AF) 54 55 #define STM32MP1_REV_B U(0x2000) 56 #define STM32MP1_REV_Z U(0x2001) 57 58 /******************************************************************************* 59 * PACKAGE ID 60 ******************************************************************************/ 61 #define PKG_AA_LFBGA448 U(4) 62 #define PKG_AB_LFBGA354 U(3) 63 #define PKG_AC_TFBGA361 U(2) 64 #define PKG_AD_TFBGA257 U(1) 65 66 /******************************************************************************* 67 * STM32MP1 memory map related constants 68 ******************************************************************************/ 69 #define STM32MP_ROM_BASE U(0x00000000) 70 #define STM32MP_ROM_SIZE U(0x00020000) 71 72 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 75 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 76 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 77 STM32MP_SYSRAM_SIZE - \ 78 STM32MP_NS_SYSRAM_SIZE) 79 80 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 81 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 82 83 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 84 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 85 STM32MP_NS_SYSRAM_SIZE) 86 87 /* DDR configuration */ 88 #define STM32MP_DDR_BASE U(0xC0000000) 89 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 90 91 /* DDR power initializations */ 92 #ifndef __ASSEMBLER__ 93 enum ddr_type { 94 STM32MP_DDR3, 95 STM32MP_LPDDR2, 96 STM32MP_LPDDR3 97 }; 98 #endif 99 100 /* Section used inside TF binaries */ 101 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 102 /* 256 Octets reserved for header */ 103 #define STM32MP_HEADER_SIZE U(0x00000100) 104 105 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 106 STM32MP_PARAM_LOAD_SIZE + \ 107 STM32MP_HEADER_SIZE) 108 109 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 110 (STM32MP_PARAM_LOAD_SIZE + \ 111 STM32MP_HEADER_SIZE)) 112 113 /* BL2 and BL32/sp_min require 4 tables */ 114 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 115 116 /* 117 * MAX_MMAP_REGIONS is usually: 118 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 119 */ 120 #if defined(IMAGE_BL2) 121 #define MAX_MMAP_REGIONS 11 122 #endif 123 124 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 125 #define STM32MP_BL33_MAX_SIZE U(0x400000) 126 127 /* Define maximum page size for NAND devices */ 128 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 129 130 /******************************************************************************* 131 * STM32MP1 device/io map related constants (used for MMU) 132 ******************************************************************************/ 133 #define STM32MP1_DEVICE1_BASE U(0x40000000) 134 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 135 136 #define STM32MP1_DEVICE2_BASE U(0x80000000) 137 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 138 139 /******************************************************************************* 140 * STM32MP1 RCC 141 ******************************************************************************/ 142 #define RCC_BASE U(0x50000000) 143 144 /******************************************************************************* 145 * STM32MP1 PWR 146 ******************************************************************************/ 147 #define PWR_BASE U(0x50001000) 148 149 /******************************************************************************* 150 * STM32MP1 GPIO 151 ******************************************************************************/ 152 #define GPIOA_BASE U(0x50002000) 153 #define GPIOB_BASE U(0x50003000) 154 #define GPIOC_BASE U(0x50004000) 155 #define GPIOD_BASE U(0x50005000) 156 #define GPIOE_BASE U(0x50006000) 157 #define GPIOF_BASE U(0x50007000) 158 #define GPIOG_BASE U(0x50008000) 159 #define GPIOH_BASE U(0x50009000) 160 #define GPIOI_BASE U(0x5000A000) 161 #define GPIOJ_BASE U(0x5000B000) 162 #define GPIOK_BASE U(0x5000C000) 163 #define GPIOZ_BASE U(0x54004000) 164 #define GPIO_BANK_OFFSET U(0x1000) 165 166 /* Bank IDs used in GPIO driver API */ 167 #define GPIO_BANK_A U(0) 168 #define GPIO_BANK_B U(1) 169 #define GPIO_BANK_C U(2) 170 #define GPIO_BANK_D U(3) 171 #define GPIO_BANK_E U(4) 172 #define GPIO_BANK_F U(5) 173 #define GPIO_BANK_G U(6) 174 #define GPIO_BANK_H U(7) 175 #define GPIO_BANK_I U(8) 176 #define GPIO_BANK_J U(9) 177 #define GPIO_BANK_K U(10) 178 #define GPIO_BANK_Z U(25) 179 180 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 181 182 /******************************************************************************* 183 * STM32MP1 UART 184 ******************************************************************************/ 185 #define USART1_BASE U(0x5C000000) 186 #define USART2_BASE U(0x4000E000) 187 #define USART3_BASE U(0x4000F000) 188 #define UART4_BASE U(0x40010000) 189 #define UART5_BASE U(0x40011000) 190 #define USART6_BASE U(0x44003000) 191 #define UART7_BASE U(0x40018000) 192 #define UART8_BASE U(0x40019000) 193 #define STM32MP_UART_BAUDRATE U(115200) 194 195 /* For UART crash console */ 196 #define STM32MP_DEBUG_USART_BASE UART4_BASE 197 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 198 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 199 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 200 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 201 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 202 #define DEBUG_UART_TX_GPIO_PORT 11 203 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 204 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 205 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 206 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 207 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 208 209 /******************************************************************************* 210 * STM32MP1 ETZPC 211 ******************************************************************************/ 212 #define STM32MP1_ETZPC_BASE U(0x5C007000) 213 214 /* ETZPC TZMA IDs */ 215 #define STM32MP1_ETZPC_TZMA_ROM U(0) 216 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 217 218 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 219 220 /* ETZPC DECPROT IDs */ 221 #define STM32MP1_ETZPC_STGENC_ID 0 222 #define STM32MP1_ETZPC_BKPSRAM_ID 1 223 #define STM32MP1_ETZPC_IWDG1_ID 2 224 #define STM32MP1_ETZPC_USART1_ID 3 225 #define STM32MP1_ETZPC_SPI6_ID 4 226 #define STM32MP1_ETZPC_I2C4_ID 5 227 #define STM32MP1_ETZPC_RNG1_ID 7 228 #define STM32MP1_ETZPC_HASH1_ID 8 229 #define STM32MP1_ETZPC_CRYP1_ID 9 230 #define STM32MP1_ETZPC_DDRCTRL_ID 10 231 #define STM32MP1_ETZPC_DDRPHYC_ID 11 232 #define STM32MP1_ETZPC_I2C6_ID 12 233 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 234 235 #define STM32MP1_ETZPC_TIM2_ID 16 236 #define STM32MP1_ETZPC_TIM3_ID 17 237 #define STM32MP1_ETZPC_TIM4_ID 18 238 #define STM32MP1_ETZPC_TIM5_ID 19 239 #define STM32MP1_ETZPC_TIM6_ID 20 240 #define STM32MP1_ETZPC_TIM7_ID 21 241 #define STM32MP1_ETZPC_TIM12_ID 22 242 #define STM32MP1_ETZPC_TIM13_ID 23 243 #define STM32MP1_ETZPC_TIM14_ID 24 244 #define STM32MP1_ETZPC_LPTIM1_ID 25 245 #define STM32MP1_ETZPC_WWDG1_ID 26 246 #define STM32MP1_ETZPC_SPI2_ID 27 247 #define STM32MP1_ETZPC_SPI3_ID 28 248 #define STM32MP1_ETZPC_SPDIFRX_ID 29 249 #define STM32MP1_ETZPC_USART2_ID 30 250 #define STM32MP1_ETZPC_USART3_ID 31 251 #define STM32MP1_ETZPC_UART4_ID 32 252 #define STM32MP1_ETZPC_UART5_ID 33 253 #define STM32MP1_ETZPC_I2C1_ID 34 254 #define STM32MP1_ETZPC_I2C2_ID 35 255 #define STM32MP1_ETZPC_I2C3_ID 36 256 #define STM32MP1_ETZPC_I2C5_ID 37 257 #define STM32MP1_ETZPC_CEC_ID 38 258 #define STM32MP1_ETZPC_DAC_ID 39 259 #define STM32MP1_ETZPC_UART7_ID 40 260 #define STM32MP1_ETZPC_UART8_ID 41 261 #define STM32MP1_ETZPC_MDIOS_ID 44 262 #define STM32MP1_ETZPC_TIM1_ID 48 263 #define STM32MP1_ETZPC_TIM8_ID 49 264 #define STM32MP1_ETZPC_USART6_ID 51 265 #define STM32MP1_ETZPC_SPI1_ID 52 266 #define STM32MP1_ETZPC_SPI4_ID 53 267 #define STM32MP1_ETZPC_TIM15_ID 54 268 #define STM32MP1_ETZPC_TIM16_ID 55 269 #define STM32MP1_ETZPC_TIM17_ID 56 270 #define STM32MP1_ETZPC_SPI5_ID 57 271 #define STM32MP1_ETZPC_SAI1_ID 58 272 #define STM32MP1_ETZPC_SAI2_ID 59 273 #define STM32MP1_ETZPC_SAI3_ID 60 274 #define STM32MP1_ETZPC_DFSDM_ID 61 275 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 276 #define STM32MP1_ETZPC_LPTIM2_ID 64 277 #define STM32MP1_ETZPC_LPTIM3_ID 65 278 #define STM32MP1_ETZPC_LPTIM4_ID 66 279 #define STM32MP1_ETZPC_LPTIM5_ID 67 280 #define STM32MP1_ETZPC_SAI4_ID 68 281 #define STM32MP1_ETZPC_VREFBUF_ID 69 282 #define STM32MP1_ETZPC_DCMI_ID 70 283 #define STM32MP1_ETZPC_CRC2_ID 71 284 #define STM32MP1_ETZPC_ADC_ID 72 285 #define STM32MP1_ETZPC_HASH2_ID 73 286 #define STM32MP1_ETZPC_RNG2_ID 74 287 #define STM32MP1_ETZPC_CRYP2_ID 75 288 #define STM32MP1_ETZPC_SRAM1_ID 80 289 #define STM32MP1_ETZPC_SRAM2_ID 81 290 #define STM32MP1_ETZPC_SRAM3_ID 82 291 #define STM32MP1_ETZPC_SRAM4_ID 83 292 #define STM32MP1_ETZPC_RETRAM_ID 84 293 #define STM32MP1_ETZPC_OTG_ID 85 294 #define STM32MP1_ETZPC_SDMMC3_ID 86 295 #define STM32MP1_ETZPC_DLYBSD3_ID 87 296 #define STM32MP1_ETZPC_DMA1_ID 88 297 #define STM32MP1_ETZPC_DMA2_ID 89 298 #define STM32MP1_ETZPC_DMAMUX_ID 90 299 #define STM32MP1_ETZPC_FMC_ID 91 300 #define STM32MP1_ETZPC_QSPI_ID 92 301 #define STM32MP1_ETZPC_DLYBQ_ID 93 302 #define STM32MP1_ETZPC_ETH_ID 94 303 #define STM32MP1_ETZPC_RSV_ID 95 304 305 #define STM32MP_ETZPC_MAX_ID 96 306 307 /******************************************************************************* 308 * STM32MP1 TZC (TZ400) 309 ******************************************************************************/ 310 #define STM32MP1_TZC_BASE U(0x5C006000) 311 312 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 313 TZC_400_REGION_ATTR_FILTER_BIT(1)) 314 315 /******************************************************************************* 316 * STM32MP1 SDMMC 317 ******************************************************************************/ 318 #define STM32MP_SDMMC1_BASE U(0x58005000) 319 #define STM32MP_SDMMC2_BASE U(0x58007000) 320 #define STM32MP_SDMMC3_BASE U(0x48004000) 321 322 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 323 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 324 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 325 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 326 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 327 328 /******************************************************************************* 329 * STM32MP1 BSEC / OTP 330 ******************************************************************************/ 331 #define STM32MP1_OTP_MAX_ID 0x5FU 332 #define STM32MP1_UPPER_OTP_START 0x20U 333 334 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 335 336 /* OTP offsets */ 337 #define DATA0_OTP U(0) 338 #define PART_NUMBER_OTP U(1) 339 #define NAND_OTP U(9) 340 #define PACKAGE_OTP U(16) 341 #define HW2_OTP U(18) 342 343 /* OTP mask */ 344 /* DATA0 */ 345 #define DATA0_OTP_SECURED BIT(6) 346 347 /* PART NUMBER */ 348 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 349 #define PART_NUMBER_OTP_PART_SHIFT 0 350 351 /* PACKAGE */ 352 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 353 #define PACKAGE_OTP_PKG_SHIFT 27 354 355 /* IWDG OTP */ 356 #define HW2_OTP_IWDG_HW_POS U(3) 357 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 358 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 359 360 /* HW2 OTP */ 361 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 362 363 /* NAND OTP */ 364 /* NAND parameter storage flag */ 365 #define NAND_PARAM_STORED_IN_OTP BIT(31) 366 367 /* NAND page size in bytes */ 368 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 369 #define NAND_PAGE_SIZE_SHIFT 29 370 #define NAND_PAGE_SIZE_2K U(0) 371 #define NAND_PAGE_SIZE_4K U(1) 372 #define NAND_PAGE_SIZE_8K U(2) 373 374 /* NAND block size in pages */ 375 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 376 #define NAND_BLOCK_SIZE_SHIFT 27 377 #define NAND_BLOCK_SIZE_64_PAGES U(0) 378 #define NAND_BLOCK_SIZE_128_PAGES U(1) 379 #define NAND_BLOCK_SIZE_256_PAGES U(2) 380 381 /* NAND number of block (in unit of 256 blocs) */ 382 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 383 #define NAND_BLOCK_NB_SHIFT 19 384 #define NAND_BLOCK_NB_UNIT U(256) 385 386 /* NAND bus width in bits */ 387 #define NAND_WIDTH_MASK BIT(18) 388 #define NAND_WIDTH_SHIFT 18 389 390 /* NAND number of ECC bits per 512 bytes */ 391 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 392 #define NAND_ECC_BIT_NB_SHIFT 15 393 #define NAND_ECC_BIT_NB_UNSET U(0) 394 #define NAND_ECC_BIT_NB_1_BITS U(1) 395 #define NAND_ECC_BIT_NB_4_BITS U(2) 396 #define NAND_ECC_BIT_NB_8_BITS U(3) 397 #define NAND_ECC_ON_DIE U(4) 398 399 /* NAND number of planes */ 400 #define NAND_PLANE_BIT_NB_MASK BIT(14) 401 402 /******************************************************************************* 403 * STM32MP1 TAMP 404 ******************************************************************************/ 405 #define TAMP_BASE U(0x5C00A000) 406 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 407 408 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 409 static inline uint32_t tamp_bkpr(uint32_t idx) 410 { 411 return TAMP_BKP_REGISTER_BASE + (idx << 2); 412 } 413 #endif 414 415 /******************************************************************************* 416 * STM32MP1 DDRCTRL 417 ******************************************************************************/ 418 #define DDRCTRL_BASE U(0x5A003000) 419 420 /******************************************************************************* 421 * STM32MP1 DDRPHYC 422 ******************************************************************************/ 423 #define DDRPHYC_BASE U(0x5A004000) 424 425 /******************************************************************************* 426 * STM32MP1 IWDG 427 ******************************************************************************/ 428 #define IWDG_MAX_INSTANCE U(2) 429 #define IWDG1_INST U(0) 430 #define IWDG2_INST U(1) 431 432 #define IWDG1_BASE U(0x5C003000) 433 #define IWDG2_BASE U(0x5A002000) 434 435 /******************************************************************************* 436 * Miscellaneous STM32MP1 peripherals base address 437 ******************************************************************************/ 438 #define BSEC_BASE U(0x5C005000) 439 #define CRYP1_BASE U(0x54001000) 440 #define DBGMCU_BASE U(0x50081000) 441 #define HASH1_BASE U(0x54002000) 442 #define I2C4_BASE U(0x5C002000) 443 #define I2C6_BASE U(0x5c009000) 444 #define RNG1_BASE U(0x54003000) 445 #define RTC_BASE U(0x5c004000) 446 #define SPI6_BASE U(0x5c001000) 447 #define STGEN_BASE U(0x5c008000) 448 #define SYSCFG_BASE U(0x50020000) 449 450 /******************************************************************************* 451 * Device Tree defines 452 ******************************************************************************/ 453 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 454 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 455 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 456 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 457 458 #endif /* STM32MP1_DEF_H */ 459