1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #endif 29 30 /******************************************************************************* 31 * CHIP ID 32 ******************************************************************************/ 33 #define STM32MP157C_PART_NB U(0x05000000) 34 #define STM32MP157A_PART_NB U(0x05000001) 35 #define STM32MP153C_PART_NB U(0x05000024) 36 #define STM32MP153A_PART_NB U(0x05000025) 37 #define STM32MP151C_PART_NB U(0x0500002E) 38 #define STM32MP151A_PART_NB U(0x0500002F) 39 40 #define STM32MP1_REV_B U(0x2000) 41 42 /******************************************************************************* 43 * PACKAGE ID 44 ******************************************************************************/ 45 #define PKG_AA_LFBGA448 U(4) 46 #define PKG_AB_LFBGA354 U(3) 47 #define PKG_AC_TFBGA361 U(2) 48 #define PKG_AD_TFBGA257 U(1) 49 50 /******************************************************************************* 51 * STM32MP1 memory map related constants 52 ******************************************************************************/ 53 #define STM32MP_ROM_BASE U(0x00000000) 54 #define STM32MP_ROM_SIZE U(0x00020000) 55 56 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 57 #define STM32MP_SYSRAM_SIZE U(0x00040000) 58 59 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 60 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 61 STM32MP_SYSRAM_SIZE - \ 62 STM32MP_NS_SYSRAM_SIZE) 63 64 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 65 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 66 STM32MP_NS_SYSRAM_SIZE) 67 68 /* DDR configuration */ 69 #define STM32MP_DDR_BASE U(0xC0000000) 70 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 71 #ifdef AARCH32_SP_OPTEE 72 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 73 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 74 #else 75 #define STM32MP_DDR_S_SIZE U(0) 76 #define STM32MP_DDR_SHMEM_SIZE U(0) 77 #endif 78 79 /* DDR power initializations */ 80 #ifndef __ASSEMBLER__ 81 enum ddr_type { 82 STM32MP_DDR3, 83 STM32MP_LPDDR2, 84 STM32MP_LPDDR3 85 }; 86 #endif 87 88 /* Section used inside TF binaries */ 89 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 90 /* 256 Octets reserved for header */ 91 #define STM32MP_HEADER_SIZE U(0x00000100) 92 93 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 94 STM32MP_PARAM_LOAD_SIZE + \ 95 STM32MP_HEADER_SIZE) 96 97 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 98 (STM32MP_PARAM_LOAD_SIZE + \ 99 STM32MP_HEADER_SIZE)) 100 101 #ifdef AARCH32_SP_OPTEE 102 #define STM32MP_BL32_SIZE U(0) 103 104 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 105 106 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 107 STM32MP_OPTEE_BASE) 108 #else 109 #if STACK_PROTECTOR_ENABLED 110 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 111 #else 112 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 113 #endif 114 #endif 115 116 #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ 117 STM32MP_SEC_SYSRAM_SIZE - \ 118 STM32MP_BL32_SIZE) 119 120 #ifdef AARCH32_SP_OPTEE 121 #if STACK_PROTECTOR_ENABLED 122 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 123 #else 124 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 125 #endif 126 #else 127 #if STACK_PROTECTOR_ENABLED 128 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 129 #else 130 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 131 #endif 132 #endif 133 134 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 135 STM32MP_BL2_SIZE) 136 137 /* BL2 and BL32/sp_min require 4 tables */ 138 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 139 140 /* 141 * MAX_MMAP_REGIONS is usually: 142 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 143 */ 144 #if defined(IMAGE_BL2) 145 #define MAX_MMAP_REGIONS 11 146 #endif 147 #if defined(IMAGE_BL32) 148 #define MAX_MMAP_REGIONS 6 149 #endif 150 151 /* DTB initialization value */ 152 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 153 154 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 155 STM32MP_DTB_SIZE) 156 157 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 158 159 /* Define maximum page size for NAND devices */ 160 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 161 162 /******************************************************************************* 163 * STM32MP1 RAW partition offset for MTD devices 164 ******************************************************************************/ 165 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 166 #ifdef AARCH32_SP_OPTEE 167 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 168 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 169 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 170 #endif 171 172 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 173 #ifdef AARCH32_SP_OPTEE 174 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 175 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 176 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 177 #endif 178 179 /******************************************************************************* 180 * STM32MP1 device/io map related constants (used for MMU) 181 ******************************************************************************/ 182 #define STM32MP1_DEVICE1_BASE U(0x40000000) 183 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 184 185 #define STM32MP1_DEVICE2_BASE U(0x80000000) 186 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 187 188 /******************************************************************************* 189 * STM32MP1 RCC 190 ******************************************************************************/ 191 #define RCC_BASE U(0x50000000) 192 193 /******************************************************************************* 194 * STM32MP1 PWR 195 ******************************************************************************/ 196 #define PWR_BASE U(0x50001000) 197 198 /******************************************************************************* 199 * STM32MP1 GPIO 200 ******************************************************************************/ 201 #define GPIOA_BASE U(0x50002000) 202 #define GPIOB_BASE U(0x50003000) 203 #define GPIOC_BASE U(0x50004000) 204 #define GPIOD_BASE U(0x50005000) 205 #define GPIOE_BASE U(0x50006000) 206 #define GPIOF_BASE U(0x50007000) 207 #define GPIOG_BASE U(0x50008000) 208 #define GPIOH_BASE U(0x50009000) 209 #define GPIOI_BASE U(0x5000A000) 210 #define GPIOJ_BASE U(0x5000B000) 211 #define GPIOK_BASE U(0x5000C000) 212 #define GPIOZ_BASE U(0x54004000) 213 #define GPIO_BANK_OFFSET U(0x1000) 214 215 /* Bank IDs used in GPIO driver API */ 216 #define GPIO_BANK_A U(0) 217 #define GPIO_BANK_B U(1) 218 #define GPIO_BANK_C U(2) 219 #define GPIO_BANK_D U(3) 220 #define GPIO_BANK_E U(4) 221 #define GPIO_BANK_F U(5) 222 #define GPIO_BANK_G U(6) 223 #define GPIO_BANK_H U(7) 224 #define GPIO_BANK_I U(8) 225 #define GPIO_BANK_J U(9) 226 #define GPIO_BANK_K U(10) 227 #define GPIO_BANK_Z U(25) 228 229 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 230 231 /******************************************************************************* 232 * STM32MP1 UART 233 ******************************************************************************/ 234 #define USART1_BASE U(0x5C000000) 235 #define USART2_BASE U(0x4000E000) 236 #define USART3_BASE U(0x4000F000) 237 #define UART4_BASE U(0x40010000) 238 #define UART5_BASE U(0x40011000) 239 #define USART6_BASE U(0x44003000) 240 #define UART7_BASE U(0x40018000) 241 #define UART8_BASE U(0x40019000) 242 #define STM32MP_UART_BAUDRATE U(115200) 243 244 /* For UART crash console */ 245 #define STM32MP_DEBUG_USART_BASE UART4_BASE 246 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 247 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 248 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 249 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 250 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 251 #define DEBUG_UART_TX_GPIO_PORT 11 252 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 253 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 254 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 255 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 256 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 257 258 /******************************************************************************* 259 * STM32MP1 ETZPC 260 ******************************************************************************/ 261 #define STM32MP1_ETZPC_BASE U(0x5C007000) 262 263 /* ETZPC TZMA IDs */ 264 #define STM32MP1_ETZPC_TZMA_ROM U(0) 265 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 266 267 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 268 269 /* ETZPC DECPROT IDs */ 270 #define STM32MP1_ETZPC_STGENC_ID 0 271 #define STM32MP1_ETZPC_BKPSRAM_ID 1 272 #define STM32MP1_ETZPC_IWDG1_ID 2 273 #define STM32MP1_ETZPC_USART1_ID 3 274 #define STM32MP1_ETZPC_SPI6_ID 4 275 #define STM32MP1_ETZPC_I2C4_ID 5 276 #define STM32MP1_ETZPC_RNG1_ID 7 277 #define STM32MP1_ETZPC_HASH1_ID 8 278 #define STM32MP1_ETZPC_CRYP1_ID 9 279 #define STM32MP1_ETZPC_DDRCTRL_ID 10 280 #define STM32MP1_ETZPC_DDRPHYC_ID 11 281 #define STM32MP1_ETZPC_I2C6_ID 12 282 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 283 284 #define STM32MP1_ETZPC_TIM2_ID 16 285 #define STM32MP1_ETZPC_TIM3_ID 17 286 #define STM32MP1_ETZPC_TIM4_ID 18 287 #define STM32MP1_ETZPC_TIM5_ID 19 288 #define STM32MP1_ETZPC_TIM6_ID 20 289 #define STM32MP1_ETZPC_TIM7_ID 21 290 #define STM32MP1_ETZPC_TIM12_ID 22 291 #define STM32MP1_ETZPC_TIM13_ID 23 292 #define STM32MP1_ETZPC_TIM14_ID 24 293 #define STM32MP1_ETZPC_LPTIM1_ID 25 294 #define STM32MP1_ETZPC_WWDG1_ID 26 295 #define STM32MP1_ETZPC_SPI2_ID 27 296 #define STM32MP1_ETZPC_SPI3_ID 28 297 #define STM32MP1_ETZPC_SPDIFRX_ID 29 298 #define STM32MP1_ETZPC_USART2_ID 30 299 #define STM32MP1_ETZPC_USART3_ID 31 300 #define STM32MP1_ETZPC_UART4_ID 32 301 #define STM32MP1_ETZPC_UART5_ID 33 302 #define STM32MP1_ETZPC_I2C1_ID 34 303 #define STM32MP1_ETZPC_I2C2_ID 35 304 #define STM32MP1_ETZPC_I2C3_ID 36 305 #define STM32MP1_ETZPC_I2C5_ID 37 306 #define STM32MP1_ETZPC_CEC_ID 38 307 #define STM32MP1_ETZPC_DAC_ID 39 308 #define STM32MP1_ETZPC_UART7_ID 40 309 #define STM32MP1_ETZPC_UART8_ID 41 310 #define STM32MP1_ETZPC_MDIOS_ID 44 311 #define STM32MP1_ETZPC_TIM1_ID 48 312 #define STM32MP1_ETZPC_TIM8_ID 49 313 #define STM32MP1_ETZPC_USART6_ID 51 314 #define STM32MP1_ETZPC_SPI1_ID 52 315 #define STM32MP1_ETZPC_SPI4_ID 53 316 #define STM32MP1_ETZPC_TIM15_ID 54 317 #define STM32MP1_ETZPC_TIM16_ID 55 318 #define STM32MP1_ETZPC_TIM17_ID 56 319 #define STM32MP1_ETZPC_SPI5_ID 57 320 #define STM32MP1_ETZPC_SAI1_ID 58 321 #define STM32MP1_ETZPC_SAI2_ID 59 322 #define STM32MP1_ETZPC_SAI3_ID 60 323 #define STM32MP1_ETZPC_DFSDM_ID 61 324 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 325 #define STM32MP1_ETZPC_LPTIM2_ID 64 326 #define STM32MP1_ETZPC_LPTIM3_ID 65 327 #define STM32MP1_ETZPC_LPTIM4_ID 66 328 #define STM32MP1_ETZPC_LPTIM5_ID 67 329 #define STM32MP1_ETZPC_SAI4_ID 68 330 #define STM32MP1_ETZPC_VREFBUF_ID 69 331 #define STM32MP1_ETZPC_DCMI_ID 70 332 #define STM32MP1_ETZPC_CRC2_ID 71 333 #define STM32MP1_ETZPC_ADC_ID 72 334 #define STM32MP1_ETZPC_HASH2_ID 73 335 #define STM32MP1_ETZPC_RNG2_ID 74 336 #define STM32MP1_ETZPC_CRYP2_ID 75 337 #define STM32MP1_ETZPC_SRAM1_ID 80 338 #define STM32MP1_ETZPC_SRAM2_ID 81 339 #define STM32MP1_ETZPC_SRAM3_ID 82 340 #define STM32MP1_ETZPC_SRAM4_ID 83 341 #define STM32MP1_ETZPC_RETRAM_ID 84 342 #define STM32MP1_ETZPC_OTG_ID 85 343 #define STM32MP1_ETZPC_SDMMC3_ID 86 344 #define STM32MP1_ETZPC_DLYBSD3_ID 87 345 #define STM32MP1_ETZPC_DMA1_ID 88 346 #define STM32MP1_ETZPC_DMA2_ID 89 347 #define STM32MP1_ETZPC_DMAMUX_ID 90 348 #define STM32MP1_ETZPC_FMC_ID 91 349 #define STM32MP1_ETZPC_QSPI_ID 92 350 #define STM32MP1_ETZPC_DLYBQ_ID 93 351 #define STM32MP1_ETZPC_ETH_ID 94 352 #define STM32MP1_ETZPC_RSV_ID 95 353 354 #define STM32MP_ETZPC_MAX_ID 96 355 356 /******************************************************************************* 357 * STM32MP1 TZC (TZ400) 358 ******************************************************************************/ 359 #define STM32MP1_TZC_BASE U(0x5C006000) 360 361 #define STM32MP1_TZC_A7_ID U(0) 362 #define STM32MP1_TZC_M4_ID U(1) 363 #define STM32MP1_TZC_LCD_ID U(3) 364 #define STM32MP1_TZC_GPU_ID U(4) 365 #define STM32MP1_TZC_MDMA_ID U(5) 366 #define STM32MP1_TZC_DMA_ID U(6) 367 #define STM32MP1_TZC_USB_HOST_ID U(7) 368 #define STM32MP1_TZC_USB_OTG_ID U(8) 369 #define STM32MP1_TZC_SDMMC_ID U(9) 370 #define STM32MP1_TZC_ETH_ID U(10) 371 #define STM32MP1_TZC_DAP_ID U(15) 372 373 #define STM32MP1_FILTER_BIT_ALL U(3) 374 375 /******************************************************************************* 376 * STM32MP1 SDMMC 377 ******************************************************************************/ 378 #define STM32MP_SDMMC1_BASE U(0x58005000) 379 #define STM32MP_SDMMC2_BASE U(0x58007000) 380 #define STM32MP_SDMMC3_BASE U(0x48004000) 381 382 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 383 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 384 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 385 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 386 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 387 388 /******************************************************************************* 389 * STM32MP1 BSEC / OTP 390 ******************************************************************************/ 391 #define STM32MP1_OTP_MAX_ID 0x5FU 392 #define STM32MP1_UPPER_OTP_START 0x20U 393 394 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 395 396 /* OTP offsets */ 397 #define DATA0_OTP U(0) 398 #define PART_NUMBER_OTP U(1) 399 #define NAND_OTP U(9) 400 #define PACKAGE_OTP U(16) 401 #define HW2_OTP U(18) 402 403 /* OTP mask */ 404 /* DATA0 */ 405 #define DATA0_OTP_SECURED BIT(6) 406 407 /* PART NUMBER */ 408 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 409 #define PART_NUMBER_OTP_PART_SHIFT 0 410 411 /* PACKAGE */ 412 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 413 #define PACKAGE_OTP_PKG_SHIFT 27 414 415 /* IWDG OTP */ 416 #define HW2_OTP_IWDG_HW_POS U(3) 417 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 418 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 419 420 /* HW2 OTP */ 421 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 422 423 /* NAND OTP */ 424 /* NAND parameter storage flag */ 425 #define NAND_PARAM_STORED_IN_OTP BIT(31) 426 427 /* NAND page size in bytes */ 428 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 429 #define NAND_PAGE_SIZE_SHIFT 29 430 #define NAND_PAGE_SIZE_2K U(0) 431 #define NAND_PAGE_SIZE_4K U(1) 432 #define NAND_PAGE_SIZE_8K U(2) 433 434 /* NAND block size in pages */ 435 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 436 #define NAND_BLOCK_SIZE_SHIFT 27 437 #define NAND_BLOCK_SIZE_64_PAGES U(0) 438 #define NAND_BLOCK_SIZE_128_PAGES U(1) 439 #define NAND_BLOCK_SIZE_256_PAGES U(2) 440 441 /* NAND number of block (in unit of 256 blocs) */ 442 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 443 #define NAND_BLOCK_NB_SHIFT 19 444 #define NAND_BLOCK_NB_UNIT U(256) 445 446 /* NAND bus width in bits */ 447 #define NAND_WIDTH_MASK BIT(18) 448 #define NAND_WIDTH_SHIFT 18 449 450 /* NAND number of ECC bits per 512 bytes */ 451 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 452 #define NAND_ECC_BIT_NB_SHIFT 15 453 #define NAND_ECC_BIT_NB_UNSET U(0) 454 #define NAND_ECC_BIT_NB_1_BITS U(1) 455 #define NAND_ECC_BIT_NB_4_BITS U(2) 456 #define NAND_ECC_BIT_NB_8_BITS U(3) 457 #define NAND_ECC_ON_DIE U(4) 458 459 /* NAND number of planes */ 460 #define NAND_PLANE_BIT_NB_MASK BIT(14) 461 462 /******************************************************************************* 463 * STM32MP1 TAMP 464 ******************************************************************************/ 465 #define TAMP_BASE U(0x5C00A000) 466 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 467 468 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 469 static inline uint32_t tamp_bkpr(uint32_t idx) 470 { 471 return TAMP_BKP_REGISTER_BASE + (idx << 2); 472 } 473 #endif 474 475 /******************************************************************************* 476 * STM32MP1 DDRCTRL 477 ******************************************************************************/ 478 #define DDRCTRL_BASE U(0x5A003000) 479 480 /******************************************************************************* 481 * STM32MP1 DDRPHYC 482 ******************************************************************************/ 483 #define DDRPHYC_BASE U(0x5A004000) 484 485 /******************************************************************************* 486 * STM32MP1 IWDG 487 ******************************************************************************/ 488 #define IWDG_MAX_INSTANCE U(2) 489 #define IWDG1_INST U(0) 490 #define IWDG2_INST U(1) 491 492 #define IWDG1_BASE U(0x5C003000) 493 #define IWDG2_BASE U(0x5A002000) 494 495 /******************************************************************************* 496 * STM32MP1 I2C4 497 ******************************************************************************/ 498 #define I2C4_BASE U(0x5C002000) 499 500 /******************************************************************************* 501 * STM32MP1 DBGMCU 502 ******************************************************************************/ 503 #define DBGMCU_BASE U(0x50081000) 504 505 /******************************************************************************* 506 * Device Tree defines 507 ******************************************************************************/ 508 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 509 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 510 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 511 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 512 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 513 514 #endif /* STM32MP1_DEF_H */ 515