1 /* 2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <common/debug.h> 11 #include <drivers/nand.h> 12 #include <drivers/raw_nand.h> 13 #include <drivers/spi_nand.h> 14 #include <drivers/spi_nor.h> 15 #include <lib/utils.h> 16 #include <plat/common/platform.h> 17 18 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 19 #if STM32MP13 20 void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size) 21 { 22 assert(buffer_addr != NULL); 23 assert(buf_size != NULL); 24 25 *buffer_addr = (void *)STM32MP_MTD_BUFFER; 26 *buf_size = PLATFORM_MTD_MAX_PAGE_SIZE; 27 } 28 #endif 29 30 static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) 31 { 32 uint32_t nand_param; 33 uint32_t nand2_param __maybe_unused; 34 35 /* Check if NAND parameters are stored in OTP */ 36 if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) { 37 ERROR("BSEC: NAND_OTP Error\n"); 38 return -EACCES; 39 } 40 41 if (nand_param == 0U) { 42 #if STM32MP13 43 if (is_slc) { 44 return 0; 45 } 46 #endif 47 #if STM32MP15 48 return 0; 49 #endif 50 } 51 52 if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { 53 #if STM32MP13 54 if (is_slc) { 55 goto ecc; 56 } 57 #endif 58 #if STM32MP15 59 goto ecc; 60 #endif 61 } 62 63 #if STM32MP13 64 if (stm32_get_otp_value(NAND2_OTP, &nand2_param) != 0) { 65 ERROR("BSEC: NAND_OTP Error\n"); 66 return -EACCES; 67 } 68 69 /* Check OTP configuration for this device */ 70 if ((((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND1_SNAND_NAND2) && !is_slc) || 71 (((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND2_SNAND_NAND1) && is_slc)) { 72 nand_param = nand2_param << (NAND_PAGE_SIZE_SHIFT - NAND2_PAGE_SIZE_SHIFT); 73 } 74 #endif 75 76 /* NAND parameter shall be read from OTP */ 77 if ((nand_param & NAND_WIDTH_MASK) != 0U) { 78 nand_dev->buswidth = NAND_BUS_WIDTH_16; 79 } else { 80 nand_dev->buswidth = NAND_BUS_WIDTH_8; 81 } 82 83 switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { 84 case NAND_PAGE_SIZE_2K: 85 nand_dev->page_size = 0x800U; 86 break; 87 88 case NAND_PAGE_SIZE_4K: 89 nand_dev->page_size = 0x1000U; 90 break; 91 92 case NAND_PAGE_SIZE_8K: 93 nand_dev->page_size = 0x2000U; 94 break; 95 96 default: 97 ERROR("Cannot read NAND page size\n"); 98 return -EINVAL; 99 } 100 101 switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { 102 case NAND_BLOCK_SIZE_64_PAGES: 103 nand_dev->block_size = 64U * nand_dev->page_size; 104 break; 105 106 case NAND_BLOCK_SIZE_128_PAGES: 107 nand_dev->block_size = 128U * nand_dev->page_size; 108 break; 109 110 case NAND_BLOCK_SIZE_256_PAGES: 111 nand_dev->block_size = 256U * nand_dev->page_size; 112 break; 113 114 default: 115 ERROR("Cannot read NAND block size\n"); 116 return -EINVAL; 117 } 118 119 nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> 120 NAND_BLOCK_NB_SHIFT) * 121 NAND_BLOCK_NB_UNIT * nand_dev->block_size; 122 123 ecc: 124 if (is_slc) { 125 switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> 126 NAND_ECC_BIT_NB_SHIFT) { 127 case NAND_ECC_BIT_NB_1_BITS: 128 nand_dev->ecc.max_bit_corr = 1U; 129 break; 130 131 case NAND_ECC_BIT_NB_4_BITS: 132 nand_dev->ecc.max_bit_corr = 4U; 133 break; 134 135 case NAND_ECC_BIT_NB_8_BITS: 136 nand_dev->ecc.max_bit_corr = 8U; 137 break; 138 139 case NAND_ECC_ON_DIE: 140 nand_dev->ecc.mode = NAND_ECC_ONDIE; 141 break; 142 143 default: 144 if (nand_dev->ecc.max_bit_corr == 0U) { 145 ERROR("No valid eccbit number\n"); 146 return -EINVAL; 147 } 148 } 149 } else { 150 /* Selected multiple plane NAND */ 151 if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) { 152 nand_dev->nb_planes = 2U; 153 } else { 154 nand_dev->nb_planes = 1U; 155 } 156 } 157 158 VERBOSE("OTP: Block %u Page %u Size %llu\n", nand_dev->block_size, 159 nand_dev->page_size, nand_dev->size); 160 161 return 0; 162 } 163 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 164 165 #if STM32MP_RAW_NAND 166 int plat_get_raw_nand_data(struct rawnand_device *device) 167 { 168 device->nand_dev->ecc.mode = NAND_ECC_HW; 169 device->nand_dev->ecc.size = SZ_512; 170 171 return get_data_from_otp(device->nand_dev, true); 172 } 173 #endif 174 175 #if STM32MP_SPI_NAND 176 int plat_get_spi_nand_data(struct spinand_device *device) 177 { 178 zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op)); 179 device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X; 180 device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 181 device->spi_read_cache_op.addr.nbytes = 2U; 182 device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 183 device->spi_read_cache_op.dummy.nbytes = 1U; 184 device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 185 device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 186 device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN; 187 188 return get_data_from_otp(device->nand_dev, false); 189 } 190 #endif 191 192 #if STM32MP_SPI_NOR 193 int plat_get_nor_data(struct nor_device *device) 194 { 195 device->size = SZ_64M; 196 197 zeromem(&device->read_op, sizeof(struct spi_mem_op)); 198 device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4; 199 device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 200 device->read_op.addr.nbytes = 3U; 201 device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 202 device->read_op.dummy.nbytes = 1U; 203 device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 204 device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 205 device->read_op.data.dir = SPI_MEM_DATA_IN; 206 207 return 0; 208 } 209 #endif 210