1*12e21dfdSLionel Debieve /* 2*12e21dfdSLionel Debieve * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3*12e21dfdSLionel Debieve * 4*12e21dfdSLionel Debieve * SPDX-License-Identifier: BSD-3-Clause 5*12e21dfdSLionel Debieve */ 6*12e21dfdSLionel Debieve 7*12e21dfdSLionel Debieve #include <errno.h> 8*12e21dfdSLionel Debieve 9*12e21dfdSLionel Debieve #include <drivers/nand.h> 10*12e21dfdSLionel Debieve #include <lib/utils.h> 11*12e21dfdSLionel Debieve #include <plat/common/platform.h> 12*12e21dfdSLionel Debieve 13*12e21dfdSLionel Debieve #define SZ_512 0x200U 14*12e21dfdSLionel Debieve 15*12e21dfdSLionel Debieve #if STM32MP_RAW_NAND 16*12e21dfdSLionel Debieve static int get_data_from_otp(struct nand_device *nand_dev) 17*12e21dfdSLionel Debieve { 18*12e21dfdSLionel Debieve int result; 19*12e21dfdSLionel Debieve uint32_t nand_param; 20*12e21dfdSLionel Debieve 21*12e21dfdSLionel Debieve /* Check if NAND parameters are stored in OTP */ 22*12e21dfdSLionel Debieve result = bsec_shadow_read_otp(&nand_param, NAND_OTP); 23*12e21dfdSLionel Debieve if (result != BSEC_OK) { 24*12e21dfdSLionel Debieve ERROR("BSEC: NAND_OTP Error %i\n", result); 25*12e21dfdSLionel Debieve return -EACCES; 26*12e21dfdSLionel Debieve } 27*12e21dfdSLionel Debieve 28*12e21dfdSLionel Debieve if (nand_param == 0U) { 29*12e21dfdSLionel Debieve return 0; 30*12e21dfdSLionel Debieve } 31*12e21dfdSLionel Debieve 32*12e21dfdSLionel Debieve if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { 33*12e21dfdSLionel Debieve goto ecc; 34*12e21dfdSLionel Debieve } 35*12e21dfdSLionel Debieve 36*12e21dfdSLionel Debieve /* NAND parameter shall be read from OTP */ 37*12e21dfdSLionel Debieve if ((nand_param & NAND_WIDTH_MASK) != 0U) { 38*12e21dfdSLionel Debieve nand_dev->buswidth = NAND_BUS_WIDTH_16; 39*12e21dfdSLionel Debieve } else { 40*12e21dfdSLionel Debieve nand_dev->buswidth = NAND_BUS_WIDTH_8; 41*12e21dfdSLionel Debieve } 42*12e21dfdSLionel Debieve 43*12e21dfdSLionel Debieve switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { 44*12e21dfdSLionel Debieve case NAND_PAGE_SIZE_2K: 45*12e21dfdSLionel Debieve nand_dev->page_size = 0x800U; 46*12e21dfdSLionel Debieve break; 47*12e21dfdSLionel Debieve 48*12e21dfdSLionel Debieve case NAND_PAGE_SIZE_4K: 49*12e21dfdSLionel Debieve nand_dev->page_size = 0x1000U; 50*12e21dfdSLionel Debieve break; 51*12e21dfdSLionel Debieve 52*12e21dfdSLionel Debieve case NAND_PAGE_SIZE_8K: 53*12e21dfdSLionel Debieve nand_dev->page_size = 0x2000U; 54*12e21dfdSLionel Debieve break; 55*12e21dfdSLionel Debieve 56*12e21dfdSLionel Debieve default: 57*12e21dfdSLionel Debieve ERROR("Cannot read NAND page size\n"); 58*12e21dfdSLionel Debieve return -EINVAL; 59*12e21dfdSLionel Debieve } 60*12e21dfdSLionel Debieve 61*12e21dfdSLionel Debieve switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { 62*12e21dfdSLionel Debieve case NAND_BLOCK_SIZE_64_PAGES: 63*12e21dfdSLionel Debieve nand_dev->block_size = 64U * nand_dev->page_size; 64*12e21dfdSLionel Debieve break; 65*12e21dfdSLionel Debieve 66*12e21dfdSLionel Debieve case NAND_BLOCK_SIZE_128_PAGES: 67*12e21dfdSLionel Debieve nand_dev->block_size = 128U * nand_dev->page_size; 68*12e21dfdSLionel Debieve break; 69*12e21dfdSLionel Debieve 70*12e21dfdSLionel Debieve case NAND_BLOCK_SIZE_256_PAGES: 71*12e21dfdSLionel Debieve nand_dev->block_size = 256U * nand_dev->page_size; 72*12e21dfdSLionel Debieve break; 73*12e21dfdSLionel Debieve 74*12e21dfdSLionel Debieve default: 75*12e21dfdSLionel Debieve ERROR("Cannot read NAND block size\n"); 76*12e21dfdSLionel Debieve return -EINVAL; 77*12e21dfdSLionel Debieve } 78*12e21dfdSLionel Debieve 79*12e21dfdSLionel Debieve nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> 80*12e21dfdSLionel Debieve NAND_BLOCK_NB_SHIFT) * 81*12e21dfdSLionel Debieve NAND_BLOCK_NB_UNIT * nand_dev->block_size; 82*12e21dfdSLionel Debieve 83*12e21dfdSLionel Debieve ecc: 84*12e21dfdSLionel Debieve switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> 85*12e21dfdSLionel Debieve NAND_ECC_BIT_NB_SHIFT) { 86*12e21dfdSLionel Debieve case NAND_ECC_BIT_NB_1_BITS: 87*12e21dfdSLionel Debieve nand_dev->ecc.max_bit_corr = 1U; 88*12e21dfdSLionel Debieve break; 89*12e21dfdSLionel Debieve 90*12e21dfdSLionel Debieve case NAND_ECC_BIT_NB_4_BITS: 91*12e21dfdSLionel Debieve nand_dev->ecc.max_bit_corr = 4U; 92*12e21dfdSLionel Debieve break; 93*12e21dfdSLionel Debieve 94*12e21dfdSLionel Debieve case NAND_ECC_BIT_NB_8_BITS: 95*12e21dfdSLionel Debieve nand_dev->ecc.max_bit_corr = 8U; 96*12e21dfdSLionel Debieve break; 97*12e21dfdSLionel Debieve 98*12e21dfdSLionel Debieve case NAND_ECC_ON_DIE: 99*12e21dfdSLionel Debieve nand_dev->ecc.mode = NAND_ECC_ONDIE; 100*12e21dfdSLionel Debieve break; 101*12e21dfdSLionel Debieve 102*12e21dfdSLionel Debieve default: 103*12e21dfdSLionel Debieve if (nand_dev->ecc.max_bit_corr == 0U) { 104*12e21dfdSLionel Debieve ERROR("No valid eccbit number\n"); 105*12e21dfdSLionel Debieve return -EINVAL; 106*12e21dfdSLionel Debieve } 107*12e21dfdSLionel Debieve } 108*12e21dfdSLionel Debieve 109*12e21dfdSLionel Debieve VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size, 110*12e21dfdSLionel Debieve nand_dev->page_size, nand_dev->size); 111*12e21dfdSLionel Debieve 112*12e21dfdSLionel Debieve return 0; 113*12e21dfdSLionel Debieve } 114*12e21dfdSLionel Debieve #endif 115*12e21dfdSLionel Debieve 116*12e21dfdSLionel Debieve #if STM32MP_RAW_NAND 117*12e21dfdSLionel Debieve int plat_get_raw_nand_data(struct rawnand_device *device) 118*12e21dfdSLionel Debieve { 119*12e21dfdSLionel Debieve device->nand_dev->ecc.mode = NAND_ECC_HW; 120*12e21dfdSLionel Debieve device->nand_dev->ecc.size = SZ_512; 121*12e21dfdSLionel Debieve 122*12e21dfdSLionel Debieve return get_data_from_otp(device->nand_dev); 123*12e21dfdSLionel Debieve } 124*12e21dfdSLionel Debieve #endif 125*12e21dfdSLionel Debieve 126