1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/gicv2.h> 17 #include <drivers/arm/tzc400.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/stm32_console.h> 21 #include <drivers/st/stm32_gpio.h> 22 #include <drivers/st/stm32_iwdg.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <dt-bindings/clock/stm32mp1-clks.h> 25 #include <lib/el3_runtime/context_mgmt.h> 26 #include <lib/mmio.h> 27 #include <lib/xlat_tables/xlat_tables_v2.h> 28 #include <plat/common/platform.h> 29 30 #include <platform_sp_min.h> 31 32 /****************************************************************************** 33 * Placeholder variables for copying the arguments that have been passed to 34 * BL32 from BL2. 35 ******************************************************************************/ 36 static entry_point_info_t bl33_image_ep_info; 37 38 static struct console_stm32 console; 39 40 /******************************************************************************* 41 * Interrupt handler for FIQ (secure IRQ) 42 ******************************************************************************/ 43 void sp_min_plat_fiq_handler(uint32_t id) 44 { 45 switch (id & INT_ID_MASK) { 46 case STM32MP1_IRQ_TZC400: 47 ERROR("STM32MP1_IRQ_TZC400 generated\n"); 48 panic(); 49 break; 50 case STM32MP1_IRQ_AXIERRIRQ: 51 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 52 panic(); 53 break; 54 default: 55 ERROR("SECURE IT handler not define for it : %u", id); 56 break; 57 } 58 } 59 60 /******************************************************************************* 61 * Return a pointer to the 'entry_point_info' structure of the next image for 62 * the security state specified. BL33 corresponds to the non-secure image type 63 * while BL32 corresponds to the secure image type. A NULL pointer is returned 64 * if the image does not exist. 65 ******************************************************************************/ 66 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 67 { 68 entry_point_info_t *next_image_info; 69 70 next_image_info = &bl33_image_ep_info; 71 72 if (next_image_info->pc == 0U) { 73 return NULL; 74 } 75 76 return next_image_info; 77 } 78 79 /******************************************************************************* 80 * Perform any BL32 specific platform actions. 81 ******************************************************************************/ 82 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 83 u_register_t arg2, u_register_t arg3) 84 { 85 struct dt_node_info dt_uart_info; 86 int result; 87 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 88 89 /* Imprecise aborts can be masked in NonSecure */ 90 write_scr(read_scr() | SCR_AW_BIT); 91 92 assert(params_from_bl2 != NULL); 93 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 94 assert(params_from_bl2->h.version >= VERSION_2); 95 96 bl_params_node_t *bl_params = params_from_bl2->head; 97 98 /* 99 * Copy BL33 entry point information. 100 * They are stored in Secure RAM, in BL2's address space. 101 */ 102 while (bl_params != NULL) { 103 if (bl_params->image_id == BL33_IMAGE_ID) { 104 bl33_image_ep_info = *bl_params->ep_info; 105 break; 106 } 107 108 bl_params = bl_params->next_params_info; 109 } 110 111 if (dt_open_and_check() < 0) { 112 panic(); 113 } 114 115 if (bsec_probe() != 0) { 116 panic(); 117 } 118 119 if (stm32mp1_clk_probe() < 0) { 120 panic(); 121 } 122 123 result = dt_get_stdout_uart_info(&dt_uart_info); 124 125 if ((result > 0) && (dt_uart_info.status != 0U)) { 126 if (console_stm32_register(dt_uart_info.base, 0, 127 STM32MP_UART_BAUDRATE, &console) == 128 0) { 129 panic(); 130 } 131 } 132 } 133 134 /******************************************************************************* 135 * Initialize the MMU, security and the GIC. 136 ******************************************************************************/ 137 void sp_min_platform_setup(void) 138 { 139 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 140 BL_CODE_END - BL_CODE_BASE, 141 MT_CODE | MT_SECURE); 142 143 configure_mmu(); 144 145 /* Initialize tzc400 after DDR initialization */ 146 stm32mp1_security_setup(); 147 148 generic_delay_timer_init(); 149 150 stm32mp1_gic_init(); 151 152 /* Unlock ETZPC securable peripherals */ 153 #define STM32MP1_ETZPC_BASE 0x5C007000U 154 #define ETZPC_DECPROT0 0x010U 155 mmio_write_32(STM32MP1_ETZPC_BASE + ETZPC_DECPROT0, 0xFFFFFFFF); 156 157 /* Set GPIO bank Z as non secure */ 158 for (uint32_t pin = 0U; pin < STM32MP_GPIOZ_PIN_MAX_COUNT; pin++) { 159 set_gpio_secure_cfg(GPIO_BANK_Z, pin, false); 160 } 161 162 if (stm32_iwdg_init() < 0) { 163 panic(); 164 } 165 } 166 167 void sp_min_plat_arch_setup(void) 168 { 169 } 170