1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/gicv2.h> 17 #include <drivers/arm/tzc400.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/stm32_console.h> 21 #include <drivers/st/stm32_gpio.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <dt-bindings/clock/stm32mp1-clks.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/mmio.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_sp_min.h> 30 31 /****************************************************************************** 32 * Placeholder variables for copying the arguments that have been passed to 33 * BL32 from BL2. 34 ******************************************************************************/ 35 static entry_point_info_t bl33_image_ep_info; 36 37 static struct console_stm32 console; 38 39 /******************************************************************************* 40 * Interrupt handler for FIQ (secure IRQ) 41 ******************************************************************************/ 42 void sp_min_plat_fiq_handler(uint32_t id) 43 { 44 switch (id & INT_ID_MASK) { 45 case STM32MP1_IRQ_TZC400: 46 ERROR("STM32MP1_IRQ_TZC400 generated\n"); 47 panic(); 48 break; 49 case STM32MP1_IRQ_AXIERRIRQ: 50 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 51 panic(); 52 break; 53 default: 54 ERROR("SECURE IT handler not define for it : %u", id); 55 break; 56 } 57 } 58 59 /******************************************************************************* 60 * Return a pointer to the 'entry_point_info' structure of the next image for 61 * the security state specified. BL33 corresponds to the non-secure image type 62 * while BL32 corresponds to the secure image type. A NULL pointer is returned 63 * if the image does not exist. 64 ******************************************************************************/ 65 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 66 { 67 entry_point_info_t *next_image_info; 68 69 next_image_info = &bl33_image_ep_info; 70 71 if (next_image_info->pc == 0U) { 72 return NULL; 73 } 74 75 return next_image_info; 76 } 77 78 /******************************************************************************* 79 * Perform any BL32 specific platform actions. 80 ******************************************************************************/ 81 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 82 u_register_t arg2, u_register_t arg3) 83 { 84 struct dt_node_info dt_uart_info; 85 int result; 86 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 87 88 /* Imprecise aborts can be masked in NonSecure */ 89 write_scr(read_scr() | SCR_AW_BIT); 90 91 assert(params_from_bl2 != NULL); 92 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 93 assert(params_from_bl2->h.version >= VERSION_2); 94 95 bl_params_node_t *bl_params = params_from_bl2->head; 96 97 /* 98 * Copy BL33 entry point information. 99 * They are stored in Secure RAM, in BL2's address space. 100 */ 101 while (bl_params != NULL) { 102 if (bl_params->image_id == BL33_IMAGE_ID) { 103 bl33_image_ep_info = *bl_params->ep_info; 104 break; 105 } 106 107 bl_params = bl_params->next_params_info; 108 } 109 110 if (dt_open_and_check() < 0) { 111 panic(); 112 } 113 114 if (bsec_probe() != 0) { 115 panic(); 116 } 117 118 if (stm32mp1_clk_probe() < 0) { 119 panic(); 120 } 121 122 result = dt_get_stdout_uart_info(&dt_uart_info); 123 124 if ((result > 0) && (dt_uart_info.status != 0U)) { 125 if (console_stm32_register(dt_uart_info.base, 0, 126 STM32MP_UART_BAUDRATE, &console) == 127 0) { 128 panic(); 129 } 130 } 131 } 132 133 /******************************************************************************* 134 * Initialize the MMU, security and the GIC. 135 ******************************************************************************/ 136 void sp_min_platform_setup(void) 137 { 138 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 139 BL_CODE_END - BL_CODE_BASE, 140 MT_CODE | MT_SECURE); 141 142 configure_mmu(); 143 144 /* Initialize tzc400 after DDR initialization */ 145 stm32mp1_security_setup(); 146 147 generic_delay_timer_init(); 148 149 stm32mp1_gic_init(); 150 151 /* Unlock ETZPC securable peripherals */ 152 #define STM32MP1_ETZPC_BASE 0x5C007000U 153 #define ETZPC_DECPROT0 0x010U 154 mmio_write_32(STM32MP1_ETZPC_BASE + ETZPC_DECPROT0, 0xFFFFFFFF); 155 156 /* Set GPIO bank Z as non secure */ 157 for (uint32_t pin = 0U; pin < STM32MP_GPIOZ_PIN_MAX_COUNT; pin++) { 158 set_gpio_secure_cfg(GPIO_BANK_Z, pin, false); 159 } 160 } 161 162 void sp_min_plat_arch_setup(void) 163 { 164 } 165