1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <platform_sp_min.h> 20 #include <stm32mp1_clk.h> 21 #include <stm32mp1_dt.h> 22 #include <stm32mp1_private.h> 23 #include <string.h> 24 #include <tzc400.h> 25 #include <xlat_tables_v2.h> 26 27 /****************************************************************************** 28 * Placeholder variables for copying the arguments that have been passed to 29 * BL32 from BL2. 30 ******************************************************************************/ 31 static entry_point_info_t bl33_image_ep_info; 32 33 /******************************************************************************* 34 * Interrupt handler for FIQ (secure IRQ) 35 ******************************************************************************/ 36 void sp_min_plat_fiq_handler(uint32_t id) 37 { 38 switch (id) { 39 case STM32MP1_IRQ_TZC400: 40 ERROR("STM32MP1_IRQ_TZC400 generated\n"); 41 panic(); 42 break; 43 case STM32MP1_IRQ_AXIERRIRQ: 44 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 45 panic(); 46 break; 47 default: 48 ERROR("SECURE IT handler not define for it : %i", id); 49 break; 50 } 51 } 52 53 /******************************************************************************* 54 * Return a pointer to the 'entry_point_info' structure of the next image for 55 * the security state specified. BL33 corresponds to the non-secure image type 56 * while BL32 corresponds to the secure image type. A NULL pointer is returned 57 * if the image does not exist. 58 ******************************************************************************/ 59 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 60 { 61 entry_point_info_t *next_image_info; 62 63 next_image_info = &bl33_image_ep_info; 64 65 if (next_image_info->pc == 0U) { 66 return NULL; 67 } 68 69 return next_image_info; 70 } 71 72 /******************************************************************************* 73 * Perform any BL32 specific platform actions. 74 ******************************************************************************/ 75 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 76 u_register_t arg2, u_register_t arg3) 77 { 78 struct dt_node_info dt_dev_info; 79 int result; 80 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 81 82 /* Imprecise aborts can be masked in NonSecure */ 83 write_scr(read_scr() | SCR_AW_BIT); 84 85 assert(params_from_bl2 != NULL); 86 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 87 assert(params_from_bl2->h.version >= VERSION_2); 88 89 bl_params_node_t *bl_params = params_from_bl2->head; 90 91 /* 92 * Copy BL33 entry point information. 93 * They are stored in Secure RAM, in BL2's address space. 94 */ 95 while (bl_params != NULL) { 96 if (bl_params->image_id == BL33_IMAGE_ID) { 97 bl33_image_ep_info = *bl_params->ep_info; 98 break; 99 } 100 101 bl_params = bl_params->next_params_info; 102 } 103 104 if (dt_open_and_check() < 0) { 105 panic(); 106 } 107 108 if (stm32mp1_clk_probe() < 0) { 109 panic(); 110 } 111 112 result = dt_get_stdout_uart_info(&dt_dev_info); 113 114 if ((result > 0) && dt_dev_info.status) { 115 if (console_init(dt_dev_info.base, 0, STM32MP1_UART_BAUDRATE) 116 == 0) { 117 panic(); 118 } 119 } 120 } 121 122 /******************************************************************************* 123 * Initialize the MMU, security and the GIC. 124 ******************************************************************************/ 125 void sp_min_platform_setup(void) 126 { 127 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 128 BL_CODE_END - BL_CODE_BASE, 129 MT_CODE | MT_SECURE); 130 131 configure_mmu(); 132 133 /* Initialize tzc400 after DDR initialization */ 134 stm32mp1_security_setup(); 135 136 generic_delay_timer_init(); 137 138 stm32mp1_gic_init(); 139 } 140 141 void sp_min_plat_arch_setup(void) 142 { 143 } 144