1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_dummy.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/spi_nor.h> 24 #include <drivers/st/io_mmc.h> 25 #include <drivers/st/io_stm32image.h> 26 #include <drivers/st/stm32_fmc2_nand.h> 27 #include <drivers/st/stm32_qspi.h> 28 #include <drivers/st/stm32_sdmmc2.h> 29 #include <lib/mmio.h> 30 #include <lib/utils.h> 31 #include <plat/common/platform.h> 32 33 /* IO devices */ 34 static const io_dev_connector_t *dummy_dev_con; 35 static uintptr_t dummy_dev_handle; 36 static uintptr_t dummy_dev_spec; 37 38 static uintptr_t image_dev_handle; 39 static uintptr_t storage_dev_handle; 40 41 #if STM32MP_SDMMC || STM32MP_EMMC 42 static struct mmc_device_info mmc_info; 43 static io_block_spec_t gpt_block_spec = { 44 .offset = 0, 45 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ 46 }; 47 48 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 49 50 static const io_block_dev_spec_t mmc_block_dev_spec = { 51 /* It's used as temp buffer in block driver */ 52 .buffer = { 53 .offset = (size_t)&block_buffer, 54 .length = MMC_BLOCK_SIZE, 55 }, 56 .ops = { 57 .read = mmc_read_blocks, 58 .write = NULL, 59 }, 60 .block_size = MMC_BLOCK_SIZE, 61 }; 62 63 static const io_dev_connector_t *mmc_dev_con; 64 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 65 66 #if STM32MP_SPI_NOR 67 static io_mtd_dev_spec_t spi_nor_dev_spec = { 68 .ops = { 69 .init = spi_nor_init, 70 .read = spi_nor_read, 71 }, 72 }; 73 #endif 74 75 #if STM32MP_RAW_NAND 76 static io_mtd_dev_spec_t nand_dev_spec = { 77 .ops = { 78 .init = nand_raw_init, 79 .read = nand_read, 80 }, 81 }; 82 83 static const io_dev_connector_t *nand_dev_con; 84 #endif 85 86 #if STM32MP_SPI_NAND 87 static io_mtd_dev_spec_t spi_nand_dev_spec = { 88 .ops = { 89 .init = spi_nand_init, 90 .read = nand_read, 91 }, 92 }; 93 #endif 94 95 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 96 static const io_dev_connector_t *spi_dev_con; 97 #endif 98 99 #ifdef AARCH32_SP_OPTEE 100 static const struct stm32image_part_info optee_header_partition_spec = { 101 .name = OPTEE_HEADER_IMAGE_NAME, 102 .binary_type = OPTEE_HEADER_BINARY_TYPE, 103 }; 104 105 static const struct stm32image_part_info optee_core_partition_spec = { 106 .name = OPTEE_CORE_IMAGE_NAME, 107 .binary_type = OPTEE_CORE_BINARY_TYPE, 108 }; 109 110 static const struct stm32image_part_info optee_paged_partition_spec = { 111 .name = OPTEE_PAGED_IMAGE_NAME, 112 .binary_type = OPTEE_PAGED_BINARY_TYPE, 113 }; 114 #else 115 static const io_block_spec_t bl32_block_spec = { 116 .offset = BL32_BASE, 117 .length = STM32MP_BL32_SIZE 118 }; 119 #endif 120 121 static const struct stm32image_part_info bl33_partition_spec = { 122 .name = BL33_IMAGE_NAME, 123 .binary_type = BL33_BINARY_TYPE, 124 }; 125 126 enum { 127 IMG_IDX_BL33, 128 #ifdef AARCH32_SP_OPTEE 129 IMG_IDX_OPTEE_HEADER, 130 IMG_IDX_OPTEE_CORE, 131 IMG_IDX_OPTEE_PAGED, 132 #endif 133 IMG_IDX_NUM 134 }; 135 136 static struct stm32image_device_info stm32image_dev_info_spec __unused = { 137 .lba_size = MMC_BLOCK_SIZE, 138 .part_info[IMG_IDX_BL33] = { 139 .name = BL33_IMAGE_NAME, 140 .binary_type = BL33_BINARY_TYPE, 141 }, 142 #ifdef AARCH32_SP_OPTEE 143 .part_info[IMG_IDX_OPTEE_HEADER] = { 144 .name = OPTEE_HEADER_IMAGE_NAME, 145 .binary_type = OPTEE_HEADER_BINARY_TYPE, 146 }, 147 .part_info[IMG_IDX_OPTEE_CORE] = { 148 .name = OPTEE_CORE_IMAGE_NAME, 149 .binary_type = OPTEE_CORE_BINARY_TYPE, 150 }, 151 .part_info[IMG_IDX_OPTEE_PAGED] = { 152 .name = OPTEE_PAGED_IMAGE_NAME, 153 .binary_type = OPTEE_PAGED_BINARY_TYPE, 154 }, 155 #endif 156 }; 157 158 static io_block_spec_t stm32image_block_spec = { 159 .offset = 0, 160 .length = 0, 161 }; 162 163 static const io_dev_connector_t *stm32image_dev_con __unused; 164 165 static int open_dummy(const uintptr_t spec); 166 static int open_image(const uintptr_t spec); 167 static int open_storage(const uintptr_t spec); 168 169 struct plat_io_policy { 170 uintptr_t *dev_handle; 171 uintptr_t image_spec; 172 int (*check)(const uintptr_t spec); 173 }; 174 175 static const struct plat_io_policy policies[] = { 176 #ifdef AARCH32_SP_OPTEE 177 [BL32_IMAGE_ID] = { 178 .dev_handle = &image_dev_handle, 179 .image_spec = (uintptr_t)&optee_header_partition_spec, 180 .check = open_image 181 }, 182 [BL32_EXTRA1_IMAGE_ID] = { 183 .dev_handle = &image_dev_handle, 184 .image_spec = (uintptr_t)&optee_core_partition_spec, 185 .check = open_image 186 }, 187 [BL32_EXTRA2_IMAGE_ID] = { 188 .dev_handle = &image_dev_handle, 189 .image_spec = (uintptr_t)&optee_paged_partition_spec, 190 .check = open_image 191 }, 192 #else 193 [BL32_IMAGE_ID] = { 194 .dev_handle = &dummy_dev_handle, 195 .image_spec = (uintptr_t)&bl32_block_spec, 196 .check = open_dummy 197 }, 198 #endif 199 [BL33_IMAGE_ID] = { 200 .dev_handle = &image_dev_handle, 201 .image_spec = (uintptr_t)&bl33_partition_spec, 202 .check = open_image 203 }, 204 #if STM32MP_SDMMC || STM32MP_EMMC 205 [GPT_IMAGE_ID] = { 206 .dev_handle = &storage_dev_handle, 207 .image_spec = (uintptr_t)&gpt_block_spec, 208 .check = open_storage 209 }, 210 #endif 211 [STM32_IMAGE_ID] = { 212 .dev_handle = &storage_dev_handle, 213 .image_spec = (uintptr_t)&stm32image_block_spec, 214 .check = open_storage 215 } 216 }; 217 218 static int open_dummy(const uintptr_t spec) 219 { 220 return io_dev_init(dummy_dev_handle, 0); 221 } 222 223 static int open_image(const uintptr_t spec) 224 { 225 return io_dev_init(image_dev_handle, 0); 226 } 227 228 static int open_storage(const uintptr_t spec) 229 { 230 return io_dev_init(storage_dev_handle, 0); 231 } 232 233 static void print_boot_device(boot_api_context_t *boot_context) 234 { 235 switch (boot_context->boot_interface_selected) { 236 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 237 INFO("Using SDMMC\n"); 238 break; 239 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 240 INFO("Using EMMC\n"); 241 break; 242 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 243 INFO("Using QSPI NOR\n"); 244 break; 245 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 246 INFO("Using FMC NAND\n"); 247 break; 248 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 249 INFO("Using SPI NAND\n"); 250 break; 251 default: 252 ERROR("Boot interface not found\n"); 253 panic(); 254 break; 255 } 256 257 if (boot_context->boot_interface_instance != 0U) { 258 INFO(" Instance %d\n", boot_context->boot_interface_instance); 259 } 260 } 261 262 #if STM32MP_SDMMC || STM32MP_EMMC 263 static void boot_mmc(enum mmc_device_type mmc_dev_type, 264 uint16_t boot_interface_instance) 265 { 266 int io_result __unused; 267 uint8_t idx; 268 struct stm32image_part_info *part; 269 struct stm32_sdmmc2_params params; 270 const partition_entry_t *entry; 271 272 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 273 274 mmc_info.mmc_dev_type = mmc_dev_type; 275 276 switch (boot_interface_instance) { 277 case 1: 278 params.reg_base = STM32MP_SDMMC1_BASE; 279 break; 280 case 2: 281 params.reg_base = STM32MP_SDMMC2_BASE; 282 break; 283 case 3: 284 params.reg_base = STM32MP_SDMMC3_BASE; 285 break; 286 default: 287 WARN("SDMMC instance not found, using default\n"); 288 if (mmc_dev_type == MMC_IS_SD) { 289 params.reg_base = STM32MP_SDMMC1_BASE; 290 } else { 291 params.reg_base = STM32MP_SDMMC2_BASE; 292 } 293 break; 294 } 295 296 params.device_info = &mmc_info; 297 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 298 ERROR("SDMMC%u init failed\n", boot_interface_instance); 299 panic(); 300 } 301 302 /* Open MMC as a block device to read GPT table */ 303 io_result = register_io_dev_block(&mmc_dev_con); 304 if (io_result != 0) { 305 panic(); 306 } 307 308 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 309 &storage_dev_handle); 310 assert(io_result == 0); 311 312 partition_init(GPT_IMAGE_ID); 313 314 io_result = io_dev_close(storage_dev_handle); 315 assert(io_result == 0); 316 317 stm32image_dev_info_spec.device_size = 318 stm32_sdmmc2_mmc_get_device_size(); 319 320 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { 321 part = &stm32image_dev_info_spec.part_info[idx]; 322 entry = get_partition_entry(part->name); 323 if (entry == NULL) { 324 ERROR("Partition %s not found\n", part->name); 325 panic(); 326 } 327 328 part->part_offset = entry->start; 329 part->bkp_offset = 0U; 330 } 331 332 /* 333 * Re-open MMC with io_mmc, for better perfs compared to 334 * io_block. 335 */ 336 io_result = register_io_dev_mmc(&mmc_dev_con); 337 assert(io_result == 0); 338 339 io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle); 340 assert(io_result == 0); 341 342 io_result = register_io_dev_stm32image(&stm32image_dev_con); 343 assert(io_result == 0); 344 345 io_result = io_dev_open(stm32image_dev_con, 346 (uintptr_t)&stm32image_dev_info_spec, 347 &image_dev_handle); 348 assert(io_result == 0); 349 } 350 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 351 352 #if STM32MP_SPI_NOR 353 static void boot_spi_nor(boot_api_context_t *boot_context) 354 { 355 int io_result __unused; 356 uint8_t idx; 357 struct stm32image_part_info *part; 358 359 io_result = stm32_qspi_init(); 360 assert(io_result == 0); 361 362 io_result = register_io_dev_mtd(&spi_dev_con); 363 assert(io_result == 0); 364 365 /* Open connections to device */ 366 io_result = io_dev_open(spi_dev_con, 367 (uintptr_t)&spi_nor_dev_spec, 368 &storage_dev_handle); 369 assert(io_result == 0); 370 371 stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; 372 373 idx = IMG_IDX_BL33; 374 part = &stm32image_dev_info_spec.part_info[idx]; 375 part->part_offset = STM32MP_NOR_BL33_OFFSET; 376 part->bkp_offset = 0U; 377 378 #ifdef AARCH32_SP_OPTEE 379 idx = IMG_IDX_OPTEE_HEADER; 380 part = &stm32image_dev_info_spec.part_info[idx]; 381 part->part_offset = STM32MP_NOR_TEEH_OFFSET; 382 part->bkp_offset = 0U; 383 384 idx = IMG_IDX_OPTEE_PAGED; 385 part = &stm32image_dev_info_spec.part_info[idx]; 386 part->part_offset = STM32MP_NOR_TEED_OFFSET; 387 part->bkp_offset = 0U; 388 389 idx = IMG_IDX_OPTEE_CORE; 390 part = &stm32image_dev_info_spec.part_info[idx]; 391 part->part_offset = STM32MP_NOR_TEEX_OFFSET; 392 part->bkp_offset = 0U; 393 #endif 394 395 io_result = register_io_dev_stm32image(&stm32image_dev_con); 396 assert(io_result == 0); 397 398 io_result = io_dev_open(stm32image_dev_con, 399 (uintptr_t)&stm32image_dev_info_spec, 400 &image_dev_handle); 401 assert(io_result == 0); 402 } 403 #endif /* STM32MP_SPI_NOR */ 404 405 #if STM32MP_RAW_NAND 406 static void boot_fmc2_nand(boot_api_context_t *boot_context) 407 { 408 int io_result __unused; 409 uint8_t idx; 410 struct stm32image_part_info *part; 411 412 io_result = stm32_fmc2_init(); 413 assert(io_result == 0); 414 415 /* Register the IO device on this platform */ 416 io_result = register_io_dev_mtd(&nand_dev_con); 417 assert(io_result == 0); 418 419 /* Open connections to device */ 420 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 421 &storage_dev_handle); 422 assert(io_result == 0); 423 424 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; 425 426 idx = IMG_IDX_BL33; 427 part = &stm32image_dev_info_spec.part_info[idx]; 428 part->part_offset = STM32MP_NAND_BL33_OFFSET; 429 part->bkp_offset = nand_dev_spec.erase_size; 430 431 #ifdef AARCH32_SP_OPTEE 432 idx = IMG_IDX_OPTEE_HEADER; 433 part = &stm32image_dev_info_spec.part_info[idx]; 434 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 435 part->bkp_offset = nand_dev_spec.erase_size; 436 437 idx = IMG_IDX_OPTEE_PAGED; 438 part = &stm32image_dev_info_spec.part_info[idx]; 439 part->part_offset = STM32MP_NAND_TEED_OFFSET; 440 part->bkp_offset = nand_dev_spec.erase_size; 441 442 idx = IMG_IDX_OPTEE_CORE; 443 part = &stm32image_dev_info_spec.part_info[idx]; 444 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 445 part->bkp_offset = nand_dev_spec.erase_size; 446 #endif 447 448 io_result = register_io_dev_stm32image(&stm32image_dev_con); 449 assert(io_result == 0); 450 451 io_result = io_dev_open(stm32image_dev_con, 452 (uintptr_t)&stm32image_dev_info_spec, 453 &image_dev_handle); 454 assert(io_result == 0); 455 } 456 #endif /* STM32MP_RAW_NAND */ 457 458 #if STM32MP_SPI_NAND 459 static void boot_spi_nand(boot_api_context_t *boot_context) 460 { 461 int io_result __unused; 462 uint8_t idx; 463 struct stm32image_part_info *part; 464 465 io_result = stm32_qspi_init(); 466 assert(io_result == 0); 467 468 io_result = register_io_dev_mtd(&spi_dev_con); 469 assert(io_result == 0); 470 471 /* Open connections to device */ 472 io_result = io_dev_open(spi_dev_con, 473 (uintptr_t)&spi_nand_dev_spec, 474 &storage_dev_handle); 475 assert(io_result == 0); 476 477 stm32image_dev_info_spec.device_size = 478 spi_nand_dev_spec.device_size; 479 480 idx = IMG_IDX_BL33; 481 part = &stm32image_dev_info_spec.part_info[idx]; 482 part->part_offset = STM32MP_NAND_BL33_OFFSET; 483 part->bkp_offset = spi_nand_dev_spec.erase_size; 484 485 #ifdef AARCH32_SP_OPTEE 486 idx = IMG_IDX_OPTEE_HEADER; 487 part = &stm32image_dev_info_spec.part_info[idx]; 488 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 489 part->bkp_offset = spi_nand_dev_spec.erase_size; 490 491 idx = IMG_IDX_OPTEE_PAGED; 492 part = &stm32image_dev_info_spec.part_info[idx]; 493 part->part_offset = STM32MP_NAND_TEED_OFFSET; 494 part->bkp_offset = spi_nand_dev_spec.erase_size; 495 496 idx = IMG_IDX_OPTEE_CORE; 497 part = &stm32image_dev_info_spec.part_info[idx]; 498 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 499 part->bkp_offset = spi_nand_dev_spec.erase_size; 500 #endif 501 502 io_result = register_io_dev_stm32image(&stm32image_dev_con); 503 assert(io_result == 0); 504 505 io_result = io_dev_open(stm32image_dev_con, 506 (uintptr_t)&stm32image_dev_info_spec, 507 &image_dev_handle); 508 assert(io_result == 0); 509 } 510 #endif /* STM32MP_SPI_NAND */ 511 512 void stm32mp_io_setup(void) 513 { 514 int io_result __unused; 515 boot_api_context_t *boot_context = 516 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 517 518 print_boot_device(boot_context); 519 520 if ((boot_context->boot_partition_used_toboot == 1U) || 521 (boot_context->boot_partition_used_toboot == 2U)) { 522 INFO("Boot used partition fsbl%d\n", 523 boot_context->boot_partition_used_toboot); 524 } 525 526 io_result = register_io_dev_dummy(&dummy_dev_con); 527 assert(io_result == 0); 528 529 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, 530 &dummy_dev_handle); 531 assert(io_result == 0); 532 533 switch (boot_context->boot_interface_selected) { 534 #if STM32MP_SDMMC 535 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 536 dmbsy(); 537 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 538 break; 539 #endif 540 #if STM32MP_EMMC 541 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 542 dmbsy(); 543 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 544 break; 545 #endif 546 #if STM32MP_SPI_NOR 547 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 548 dmbsy(); 549 boot_spi_nor(boot_context); 550 break; 551 #endif 552 #if STM32MP_RAW_NAND 553 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 554 dmbsy(); 555 boot_fmc2_nand(boot_context); 556 break; 557 #endif 558 #if STM32MP_SPI_NAND 559 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 560 dmbsy(); 561 boot_spi_nand(boot_context); 562 break; 563 #endif 564 565 default: 566 ERROR("Boot interface %d not supported\n", 567 boot_context->boot_interface_selected); 568 break; 569 } 570 } 571 572 /* 573 * Return an IO device handle and specification which can be used to access 574 * an image. Use this to enforce platform load policy. 575 */ 576 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 577 uintptr_t *image_spec) 578 { 579 int rc; 580 const struct plat_io_policy *policy; 581 582 assert(image_id < ARRAY_SIZE(policies)); 583 584 policy = &policies[image_id]; 585 rc = policy->check(policy->image_spec); 586 if (rc == 0) { 587 *image_spec = policy->image_spec; 588 *dev_handle = *(policy->dev_handle); 589 } 590 591 return rc; 592 } 593