1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_dummy.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/spi_nor.h> 24 #include <drivers/st/io_mmc.h> 25 #include <drivers/st/io_stm32image.h> 26 #include <drivers/st/stm32_fmc2_nand.h> 27 #include <drivers/st/stm32_qspi.h> 28 #include <drivers/st/stm32_sdmmc2.h> 29 #include <lib/mmio.h> 30 #include <lib/utils.h> 31 #include <plat/common/platform.h> 32 33 /* IO devices */ 34 static const io_dev_connector_t *dummy_dev_con; 35 static uintptr_t dummy_dev_handle; 36 static uintptr_t dummy_dev_spec; 37 38 static uintptr_t image_dev_handle; 39 static uintptr_t storage_dev_handle; 40 41 #if STM32MP_SDMMC || STM32MP_EMMC 42 static struct mmc_device_info mmc_info; 43 static io_block_spec_t gpt_block_spec = { 44 .offset = 0, 45 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ 46 }; 47 48 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 49 50 static const io_block_dev_spec_t mmc_block_dev_spec = { 51 /* It's used as temp buffer in block driver */ 52 .buffer = { 53 .offset = (size_t)&block_buffer, 54 .length = MMC_BLOCK_SIZE, 55 }, 56 .ops = { 57 .read = mmc_read_blocks, 58 .write = NULL, 59 }, 60 .block_size = MMC_BLOCK_SIZE, 61 }; 62 63 static const io_dev_connector_t *mmc_dev_con; 64 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 65 66 #if STM32MP_SPI_NOR 67 static io_mtd_dev_spec_t spi_nor_dev_spec = { 68 .ops = { 69 .init = spi_nor_init, 70 .read = spi_nor_read, 71 }, 72 }; 73 #endif 74 75 #if STM32MP_RAW_NAND 76 static io_mtd_dev_spec_t nand_dev_spec = { 77 .ops = { 78 .init = nand_raw_init, 79 .read = nand_read, 80 }, 81 }; 82 83 static const io_dev_connector_t *nand_dev_con; 84 #endif 85 86 #if STM32MP_SPI_NAND 87 static io_mtd_dev_spec_t spi_nand_dev_spec = { 88 .ops = { 89 .init = spi_nand_init, 90 .read = nand_read, 91 }, 92 }; 93 #endif 94 95 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 96 static const io_dev_connector_t *spi_dev_con; 97 #endif 98 99 #ifdef AARCH32_SP_OPTEE 100 static const struct stm32image_part_info optee_header_partition_spec = { 101 .name = OPTEE_HEADER_IMAGE_NAME, 102 .binary_type = OPTEE_HEADER_BINARY_TYPE, 103 }; 104 105 static const struct stm32image_part_info optee_pager_partition_spec = { 106 .name = OPTEE_PAGER_IMAGE_NAME, 107 .binary_type = OPTEE_PAGER_BINARY_TYPE, 108 }; 109 110 static const struct stm32image_part_info optee_paged_partition_spec = { 111 .name = OPTEE_PAGED_IMAGE_NAME, 112 .binary_type = OPTEE_PAGED_BINARY_TYPE, 113 }; 114 #else 115 static const io_block_spec_t bl32_block_spec = { 116 .offset = BL32_BASE, 117 .length = STM32MP_BL32_SIZE 118 }; 119 #endif 120 121 static const io_block_spec_t bl2_block_spec = { 122 .offset = BL2_BASE, 123 .length = STM32MP_BL2_SIZE, 124 }; 125 126 static const struct stm32image_part_info bl33_partition_spec = { 127 .name = BL33_IMAGE_NAME, 128 .binary_type = BL33_BINARY_TYPE, 129 }; 130 131 enum { 132 IMG_IDX_BL33, 133 #ifdef AARCH32_SP_OPTEE 134 IMG_IDX_OPTEE_HEADER, 135 IMG_IDX_OPTEE_PAGER, 136 IMG_IDX_OPTEE_PAGED, 137 #endif 138 IMG_IDX_NUM 139 }; 140 141 static struct stm32image_device_info stm32image_dev_info_spec __unused = { 142 .lba_size = MMC_BLOCK_SIZE, 143 .part_info[IMG_IDX_BL33] = { 144 .name = BL33_IMAGE_NAME, 145 .binary_type = BL33_BINARY_TYPE, 146 }, 147 #ifdef AARCH32_SP_OPTEE 148 .part_info[IMG_IDX_OPTEE_HEADER] = { 149 .name = OPTEE_HEADER_IMAGE_NAME, 150 .binary_type = OPTEE_HEADER_BINARY_TYPE, 151 }, 152 .part_info[IMG_IDX_OPTEE_PAGER] = { 153 .name = OPTEE_PAGER_IMAGE_NAME, 154 .binary_type = OPTEE_PAGER_BINARY_TYPE, 155 }, 156 .part_info[IMG_IDX_OPTEE_PAGED] = { 157 .name = OPTEE_PAGED_IMAGE_NAME, 158 .binary_type = OPTEE_PAGED_BINARY_TYPE, 159 }, 160 #endif 161 }; 162 163 static io_block_spec_t stm32image_block_spec = { 164 .offset = 0, 165 .length = 0, 166 }; 167 168 static const io_dev_connector_t *stm32image_dev_con __unused; 169 170 static int open_dummy(const uintptr_t spec); 171 static int open_image(const uintptr_t spec); 172 static int open_storage(const uintptr_t spec); 173 174 struct plat_io_policy { 175 uintptr_t *dev_handle; 176 uintptr_t image_spec; 177 int (*check)(const uintptr_t spec); 178 }; 179 180 static const struct plat_io_policy policies[] = { 181 [BL2_IMAGE_ID] = { 182 .dev_handle = &dummy_dev_handle, 183 .image_spec = (uintptr_t)&bl2_block_spec, 184 .check = open_dummy 185 }, 186 #ifdef AARCH32_SP_OPTEE 187 [BL32_IMAGE_ID] = { 188 .dev_handle = &image_dev_handle, 189 .image_spec = (uintptr_t)&optee_header_partition_spec, 190 .check = open_image 191 }, 192 [BL32_EXTRA1_IMAGE_ID] = { 193 .dev_handle = &image_dev_handle, 194 .image_spec = (uintptr_t)&optee_pager_partition_spec, 195 .check = open_image 196 }, 197 [BL32_EXTRA2_IMAGE_ID] = { 198 .dev_handle = &image_dev_handle, 199 .image_spec = (uintptr_t)&optee_paged_partition_spec, 200 .check = open_image 201 }, 202 #else 203 [BL32_IMAGE_ID] = { 204 .dev_handle = &dummy_dev_handle, 205 .image_spec = (uintptr_t)&bl32_block_spec, 206 .check = open_dummy 207 }, 208 #endif 209 [BL33_IMAGE_ID] = { 210 .dev_handle = &image_dev_handle, 211 .image_spec = (uintptr_t)&bl33_partition_spec, 212 .check = open_image 213 }, 214 #if STM32MP_SDMMC || STM32MP_EMMC 215 [GPT_IMAGE_ID] = { 216 .dev_handle = &storage_dev_handle, 217 .image_spec = (uintptr_t)&gpt_block_spec, 218 .check = open_storage 219 }, 220 #endif 221 [STM32_IMAGE_ID] = { 222 .dev_handle = &storage_dev_handle, 223 .image_spec = (uintptr_t)&stm32image_block_spec, 224 .check = open_storage 225 } 226 }; 227 228 static int open_dummy(const uintptr_t spec) 229 { 230 return io_dev_init(dummy_dev_handle, 0); 231 } 232 233 static int open_image(const uintptr_t spec) 234 { 235 return io_dev_init(image_dev_handle, 0); 236 } 237 238 static int open_storage(const uintptr_t spec) 239 { 240 return io_dev_init(storage_dev_handle, 0); 241 } 242 243 static void print_boot_device(boot_api_context_t *boot_context) 244 { 245 switch (boot_context->boot_interface_selected) { 246 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 247 INFO("Using SDMMC\n"); 248 break; 249 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 250 INFO("Using EMMC\n"); 251 break; 252 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 253 INFO("Using QSPI NOR\n"); 254 break; 255 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 256 INFO("Using FMC NAND\n"); 257 break; 258 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 259 INFO("Using SPI NAND\n"); 260 break; 261 default: 262 ERROR("Boot interface not found\n"); 263 panic(); 264 break; 265 } 266 267 if (boot_context->boot_interface_instance != 0U) { 268 INFO(" Instance %d\n", boot_context->boot_interface_instance); 269 } 270 } 271 272 #if STM32MP_SDMMC || STM32MP_EMMC 273 static void boot_mmc(enum mmc_device_type mmc_dev_type, 274 uint16_t boot_interface_instance) 275 { 276 int io_result __unused; 277 uint8_t idx; 278 struct stm32image_part_info *part; 279 struct stm32_sdmmc2_params params; 280 const partition_entry_t *entry; 281 282 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 283 284 mmc_info.mmc_dev_type = mmc_dev_type; 285 286 switch (boot_interface_instance) { 287 case 1: 288 params.reg_base = STM32MP_SDMMC1_BASE; 289 break; 290 case 2: 291 params.reg_base = STM32MP_SDMMC2_BASE; 292 break; 293 case 3: 294 params.reg_base = STM32MP_SDMMC3_BASE; 295 break; 296 default: 297 WARN("SDMMC instance not found, using default\n"); 298 if (mmc_dev_type == MMC_IS_SD) { 299 params.reg_base = STM32MP_SDMMC1_BASE; 300 } else { 301 params.reg_base = STM32MP_SDMMC2_BASE; 302 } 303 break; 304 } 305 306 params.device_info = &mmc_info; 307 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 308 ERROR("SDMMC%u init failed\n", boot_interface_instance); 309 panic(); 310 } 311 312 /* Open MMC as a block device to read GPT table */ 313 io_result = register_io_dev_block(&mmc_dev_con); 314 if (io_result != 0) { 315 panic(); 316 } 317 318 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 319 &storage_dev_handle); 320 assert(io_result == 0); 321 322 partition_init(GPT_IMAGE_ID); 323 324 io_result = io_dev_close(storage_dev_handle); 325 assert(io_result == 0); 326 327 stm32image_dev_info_spec.device_size = 328 stm32_sdmmc2_mmc_get_device_size(); 329 330 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { 331 part = &stm32image_dev_info_spec.part_info[idx]; 332 entry = get_partition_entry(part->name); 333 if (entry == NULL) { 334 ERROR("Partition %s not found\n", part->name); 335 panic(); 336 } 337 338 part->part_offset = entry->start; 339 part->bkp_offset = 0U; 340 } 341 342 /* 343 * Re-open MMC with io_mmc, for better perfs compared to 344 * io_block. 345 */ 346 io_result = register_io_dev_mmc(&mmc_dev_con); 347 assert(io_result == 0); 348 349 io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle); 350 assert(io_result == 0); 351 352 io_result = register_io_dev_stm32image(&stm32image_dev_con); 353 assert(io_result == 0); 354 355 io_result = io_dev_open(stm32image_dev_con, 356 (uintptr_t)&stm32image_dev_info_spec, 357 &image_dev_handle); 358 assert(io_result == 0); 359 } 360 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 361 362 #if STM32MP_SPI_NOR 363 static void boot_spi_nor(boot_api_context_t *boot_context) 364 { 365 int io_result __unused; 366 uint8_t idx; 367 struct stm32image_part_info *part; 368 369 io_result = stm32_qspi_init(); 370 assert(io_result == 0); 371 372 io_result = register_io_dev_mtd(&spi_dev_con); 373 assert(io_result == 0); 374 375 /* Open connections to device */ 376 io_result = io_dev_open(spi_dev_con, 377 (uintptr_t)&spi_nor_dev_spec, 378 &storage_dev_handle); 379 assert(io_result == 0); 380 381 stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; 382 383 idx = IMG_IDX_BL33; 384 part = &stm32image_dev_info_spec.part_info[idx]; 385 part->part_offset = STM32MP_NOR_BL33_OFFSET; 386 part->bkp_offset = 0U; 387 388 #ifdef AARCH32_SP_OPTEE 389 idx = IMG_IDX_OPTEE_HEADER; 390 part = &stm32image_dev_info_spec.part_info[idx]; 391 part->part_offset = STM32MP_NOR_TEEH_OFFSET; 392 part->bkp_offset = 0U; 393 394 idx = IMG_IDX_OPTEE_PAGED; 395 part = &stm32image_dev_info_spec.part_info[idx]; 396 part->part_offset = STM32MP_NOR_TEED_OFFSET; 397 part->bkp_offset = 0U; 398 399 idx = IMG_IDX_OPTEE_PAGER; 400 part = &stm32image_dev_info_spec.part_info[idx]; 401 part->part_offset = STM32MP_NOR_TEEX_OFFSET; 402 part->bkp_offset = 0U; 403 #endif 404 405 io_result = register_io_dev_stm32image(&stm32image_dev_con); 406 assert(io_result == 0); 407 408 io_result = io_dev_open(stm32image_dev_con, 409 (uintptr_t)&stm32image_dev_info_spec, 410 &image_dev_handle); 411 assert(io_result == 0); 412 } 413 #endif /* STM32MP_SPI_NOR */ 414 415 #if STM32MP_RAW_NAND 416 static void boot_fmc2_nand(boot_api_context_t *boot_context) 417 { 418 int io_result __unused; 419 uint8_t idx; 420 struct stm32image_part_info *part; 421 422 io_result = stm32_fmc2_init(); 423 assert(io_result == 0); 424 425 /* Register the IO device on this platform */ 426 io_result = register_io_dev_mtd(&nand_dev_con); 427 assert(io_result == 0); 428 429 /* Open connections to device */ 430 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 431 &storage_dev_handle); 432 assert(io_result == 0); 433 434 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; 435 436 idx = IMG_IDX_BL33; 437 part = &stm32image_dev_info_spec.part_info[idx]; 438 part->part_offset = STM32MP_NAND_BL33_OFFSET; 439 part->bkp_offset = nand_dev_spec.erase_size; 440 441 #ifdef AARCH32_SP_OPTEE 442 idx = IMG_IDX_OPTEE_HEADER; 443 part = &stm32image_dev_info_spec.part_info[idx]; 444 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 445 part->bkp_offset = nand_dev_spec.erase_size; 446 447 idx = IMG_IDX_OPTEE_PAGED; 448 part = &stm32image_dev_info_spec.part_info[idx]; 449 part->part_offset = STM32MP_NAND_TEED_OFFSET; 450 part->bkp_offset = nand_dev_spec.erase_size; 451 452 idx = IMG_IDX_OPTEE_PAGER; 453 part = &stm32image_dev_info_spec.part_info[idx]; 454 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 455 part->bkp_offset = nand_dev_spec.erase_size; 456 #endif 457 458 io_result = register_io_dev_stm32image(&stm32image_dev_con); 459 assert(io_result == 0); 460 461 io_result = io_dev_open(stm32image_dev_con, 462 (uintptr_t)&stm32image_dev_info_spec, 463 &image_dev_handle); 464 assert(io_result == 0); 465 } 466 #endif /* STM32MP_RAW_NAND */ 467 468 #if STM32MP_SPI_NAND 469 static void boot_spi_nand(boot_api_context_t *boot_context) 470 { 471 int io_result __unused; 472 uint8_t idx; 473 struct stm32image_part_info *part; 474 475 io_result = stm32_qspi_init(); 476 assert(io_result == 0); 477 478 io_result = register_io_dev_mtd(&spi_dev_con); 479 assert(io_result == 0); 480 481 /* Open connections to device */ 482 io_result = io_dev_open(spi_dev_con, 483 (uintptr_t)&spi_nand_dev_spec, 484 &storage_dev_handle); 485 assert(io_result == 0); 486 487 stm32image_dev_info_spec.device_size = 488 spi_nand_dev_spec.device_size; 489 490 idx = IMG_IDX_BL33; 491 part = &stm32image_dev_info_spec.part_info[idx]; 492 part->part_offset = STM32MP_NAND_BL33_OFFSET; 493 part->bkp_offset = spi_nand_dev_spec.erase_size; 494 495 #ifdef AARCH32_SP_OPTEE 496 idx = IMG_IDX_OPTEE_HEADER; 497 part = &stm32image_dev_info_spec.part_info[idx]; 498 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 499 part->bkp_offset = spi_nand_dev_spec.erase_size; 500 501 idx = IMG_IDX_OPTEE_PAGED; 502 part = &stm32image_dev_info_spec.part_info[idx]; 503 part->part_offset = STM32MP_NAND_TEED_OFFSET; 504 part->bkp_offset = spi_nand_dev_spec.erase_size; 505 506 idx = IMG_IDX_OPTEE_PAGER; 507 part = &stm32image_dev_info_spec.part_info[idx]; 508 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 509 part->bkp_offset = spi_nand_dev_spec.erase_size; 510 #endif 511 512 io_result = register_io_dev_stm32image(&stm32image_dev_con); 513 assert(io_result == 0); 514 515 io_result = io_dev_open(stm32image_dev_con, 516 (uintptr_t)&stm32image_dev_info_spec, 517 &image_dev_handle); 518 assert(io_result == 0); 519 } 520 #endif /* STM32MP_SPI_NAND */ 521 522 void stm32mp_io_setup(void) 523 { 524 int io_result __unused; 525 boot_api_context_t *boot_context = 526 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 527 528 print_boot_device(boot_context); 529 530 if ((boot_context->boot_partition_used_toboot == 1U) || 531 (boot_context->boot_partition_used_toboot == 2U)) { 532 INFO("Boot used partition fsbl%d\n", 533 boot_context->boot_partition_used_toboot); 534 } 535 536 io_result = register_io_dev_dummy(&dummy_dev_con); 537 assert(io_result == 0); 538 539 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, 540 &dummy_dev_handle); 541 assert(io_result == 0); 542 543 switch (boot_context->boot_interface_selected) { 544 #if STM32MP_SDMMC 545 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 546 dmbsy(); 547 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 548 break; 549 #endif 550 #if STM32MP_EMMC 551 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 552 dmbsy(); 553 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 554 break; 555 #endif 556 #if STM32MP_SPI_NOR 557 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 558 dmbsy(); 559 boot_spi_nor(boot_context); 560 break; 561 #endif 562 #if STM32MP_RAW_NAND 563 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 564 dmbsy(); 565 boot_fmc2_nand(boot_context); 566 break; 567 #endif 568 #if STM32MP_SPI_NAND 569 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 570 dmbsy(); 571 boot_spi_nand(boot_context); 572 break; 573 #endif 574 575 default: 576 ERROR("Boot interface %d not supported\n", 577 boot_context->boot_interface_selected); 578 break; 579 } 580 } 581 582 /* 583 * Return an IO device handle and specification which can be used to access 584 * an image. Use this to enforce platform load policy. 585 */ 586 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 587 uintptr_t *image_spec) 588 { 589 int rc; 590 const struct plat_io_policy *policy; 591 592 assert(image_id < ARRAY_SIZE(policies)); 593 594 policy = &policies[image_id]; 595 rc = policy->check(policy->image_spec); 596 if (rc == 0) { 597 *image_spec = policy->image_spec; 598 *dev_handle = *(policy->dev_handle); 599 } 600 601 return rc; 602 } 603