1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/fwu/fwu.h> 14 #include <drivers/fwu/fwu_metadata.h> 15 #include <drivers/io/io_block.h> 16 #include <drivers/io/io_driver.h> 17 #include <drivers/io/io_encrypted.h> 18 #include <drivers/io/io_fip.h> 19 #include <drivers/io/io_memmap.h> 20 #include <drivers/io/io_mtd.h> 21 #include <drivers/io/io_storage.h> 22 #include <drivers/mmc.h> 23 #include <drivers/partition/efi.h> 24 #include <drivers/partition/partition.h> 25 #include <drivers/raw_nand.h> 26 #include <drivers/spi_nand.h> 27 #include <drivers/spi_nor.h> 28 #include <drivers/st/stm32_fmc2_nand.h> 29 #include <drivers/st/stm32_qspi.h> 30 #include <drivers/st/stm32_sdmmc2.h> 31 #include <drivers/usb_device.h> 32 #include <lib/fconf/fconf.h> 33 #include <lib/mmio.h> 34 #include <lib/utils.h> 35 #include <plat/common/platform.h> 36 #include <tools_share/firmware_image_package.h> 37 38 #include <platform_def.h> 39 #include <stm32cubeprogrammer.h> 40 #include <stm32mp_efi.h> 41 #include <stm32mp_fconf_getter.h> 42 #include <stm32mp_io_storage.h> 43 #include <usb_dfu.h> 44 45 /* IO devices */ 46 uintptr_t fip_dev_handle; 47 uintptr_t storage_dev_handle; 48 49 static const io_dev_connector_t *fip_dev_con; 50 static uint32_t nand_block_sz __maybe_unused; 51 52 #ifndef DECRYPTION_SUPPORT_none 53 static const io_dev_connector_t *enc_dev_con; 54 uintptr_t enc_dev_handle; 55 #endif 56 57 #if STM32MP_SDMMC || STM32MP_EMMC 58 static struct mmc_device_info mmc_info; 59 60 static uint8_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 61 62 static io_block_dev_spec_t mmc_block_dev_spec = { 63 /* It's used as temp buffer in block driver */ 64 .buffer = { 65 .offset = (size_t)&block_buffer, 66 .length = MMC_BLOCK_SIZE, 67 }, 68 .ops = { 69 .read = mmc_read_blocks, 70 .write = NULL, 71 }, 72 .block_size = MMC_BLOCK_SIZE, 73 }; 74 75 static const io_dev_connector_t *mmc_dev_con; 76 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 77 78 #if STM32MP_SPI_NOR 79 static io_mtd_dev_spec_t spi_nor_dev_spec = { 80 .ops = { 81 .init = spi_nor_init, 82 .read = spi_nor_read, 83 }, 84 }; 85 #endif 86 87 #if STM32MP_RAW_NAND 88 static io_mtd_dev_spec_t nand_dev_spec = { 89 .ops = { 90 .init = nand_raw_init, 91 .read = nand_read, 92 .seek = nand_seek_bb 93 }, 94 }; 95 96 static const io_dev_connector_t *nand_dev_con; 97 #endif 98 99 #if STM32MP_SPI_NAND 100 static io_mtd_dev_spec_t spi_nand_dev_spec = { 101 .ops = { 102 .init = spi_nand_init, 103 .read = nand_read, 104 .seek = nand_seek_bb 105 }, 106 }; 107 #endif 108 109 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 110 static const io_dev_connector_t *spi_dev_con; 111 #endif 112 113 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 114 static const io_dev_connector_t *memmap_dev_con; 115 #endif 116 117 io_block_spec_t image_block_spec = { 118 .offset = 0U, 119 .length = 0U, 120 }; 121 122 int open_fip(const uintptr_t spec) 123 { 124 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 125 } 126 127 #ifndef DECRYPTION_SUPPORT_none 128 int open_enc_fip(const uintptr_t spec) 129 { 130 int result; 131 uintptr_t local_image_handle; 132 133 result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID); 134 if (result != 0) { 135 return result; 136 } 137 138 result = io_open(enc_dev_handle, spec, &local_image_handle); 139 if (result != 0) { 140 return result; 141 } 142 143 VERBOSE("Using encrypted FIP\n"); 144 io_close(local_image_handle); 145 146 return 0; 147 } 148 #endif 149 150 int open_storage(const uintptr_t spec) 151 { 152 return io_dev_init(storage_dev_handle, 0); 153 } 154 155 #if STM32MP_EMMC_BOOT 156 static uint32_t get_boot_part_fip_header(void) 157 { 158 io_block_spec_t emmc_boot_fip_block_spec = { 159 .offset = STM32MP_EMMC_BOOT_FIP_OFFSET, 160 .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */ 161 }; 162 uint32_t magic = 0U; 163 int io_result; 164 size_t bytes_read; 165 uintptr_t fip_hdr_handle; 166 167 io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec, 168 &fip_hdr_handle); 169 assert(io_result == 0); 170 171 io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic), 172 &bytes_read); 173 if ((io_result != 0) || (bytes_read != sizeof(magic))) { 174 panic(); 175 } 176 177 io_close(fip_hdr_handle); 178 179 VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n", 180 __func__, magic); 181 182 return magic; 183 } 184 #endif 185 186 static void print_boot_device(boot_api_context_t *boot_context) 187 { 188 switch (boot_context->boot_interface_selected) { 189 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 190 INFO("Using SDMMC\n"); 191 break; 192 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 193 INFO("Using EMMC\n"); 194 break; 195 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 196 INFO("Using SPI NOR\n"); 197 break; 198 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 199 INFO("Using FMC NAND\n"); 200 break; 201 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 202 INFO("Using SPI NAND\n"); 203 break; 204 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 205 INFO("Using UART\n"); 206 break; 207 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 208 INFO("Using USB\n"); 209 break; 210 default: 211 ERROR("Boot interface %u not found\n", 212 boot_context->boot_interface_selected); 213 panic(); 214 break; 215 } 216 217 if (boot_context->boot_interface_instance != 0U) { 218 INFO(" Instance %d\n", boot_context->boot_interface_instance); 219 } 220 } 221 222 #if STM32MP_SDMMC || STM32MP_EMMC 223 static void boot_mmc(enum mmc_device_type mmc_dev_type, 224 uint16_t boot_interface_instance) 225 { 226 int io_result __maybe_unused; 227 struct stm32_sdmmc2_params params; 228 229 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 230 231 mmc_info.mmc_dev_type = mmc_dev_type; 232 233 switch (boot_interface_instance) { 234 case 1: 235 params.reg_base = STM32MP_SDMMC1_BASE; 236 break; 237 case 2: 238 params.reg_base = STM32MP_SDMMC2_BASE; 239 break; 240 case 3: 241 params.reg_base = STM32MP_SDMMC3_BASE; 242 break; 243 default: 244 WARN("SDMMC instance not found, using default\n"); 245 if (mmc_dev_type == MMC_IS_SD) { 246 params.reg_base = STM32MP_SDMMC1_BASE; 247 } else { 248 params.reg_base = STM32MP_SDMMC2_BASE; 249 } 250 break; 251 } 252 253 if (mmc_dev_type != MMC_IS_EMMC) { 254 params.flags = MMC_FLAG_SD_CMD6; 255 } 256 257 params.device_info = &mmc_info; 258 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 259 ERROR("SDMMC%u init failed\n", boot_interface_instance); 260 panic(); 261 } 262 263 /* Open MMC as a block device to read FIP */ 264 io_result = register_io_dev_block(&mmc_dev_con); 265 if (io_result != 0) { 266 panic(); 267 } 268 269 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 270 &storage_dev_handle); 271 assert(io_result == 0); 272 273 #if STM32MP_EMMC_BOOT 274 if (mmc_dev_type == MMC_IS_EMMC) { 275 io_result = mmc_part_switch_current_boot(); 276 assert(io_result == 0); 277 278 if (get_boot_part_fip_header() != TOC_HEADER_NAME) { 279 WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n", 280 __func__); 281 io_result = mmc_part_switch_user(); 282 assert(io_result == 0); 283 return; 284 } 285 286 VERBOSE("%s: FIP header found on eMMC boot partition\n", 287 __func__); 288 image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET; 289 image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET; 290 } 291 #endif 292 } 293 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 294 295 #if STM32MP_SPI_NOR 296 static void boot_spi_nor(boot_api_context_t *boot_context) 297 { 298 int io_result __maybe_unused; 299 300 io_result = stm32_qspi_init(); 301 assert(io_result == 0); 302 303 io_result = register_io_dev_mtd(&spi_dev_con); 304 assert(io_result == 0); 305 306 /* Open connections to device */ 307 io_result = io_dev_open(spi_dev_con, 308 (uintptr_t)&spi_nor_dev_spec, 309 &storage_dev_handle); 310 assert(io_result == 0); 311 } 312 #endif /* STM32MP_SPI_NOR */ 313 314 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 315 /* 316 * This function returns 0 if it can find an alternate 317 * image to be loaded or a negative errno otherwise. 318 */ 319 static int try_nand_backup_partitions(unsigned int image_id) 320 { 321 static unsigned int backup_id; 322 static unsigned int backup_block_nb; 323 324 /* Check if NAND storage used */ 325 if (nand_block_sz == 0U) { 326 return -ENODEV; 327 } 328 329 if (backup_id != image_id) { 330 backup_block_nb = PLATFORM_MTD_MAX_PART_SIZE / nand_block_sz; 331 backup_id = image_id; 332 } 333 334 if (backup_block_nb-- == 0U) { 335 return -ENOSPC; 336 } 337 338 #if PSA_FWU_SUPPORT 339 if (((image_block_spec.offset < STM32MP_NAND_FIP_B_OFFSET) && 340 ((image_block_spec.offset + nand_block_sz) >= STM32MP_NAND_FIP_B_OFFSET)) || 341 (image_block_spec.offset + nand_block_sz >= STM32MP_NAND_FIP_B_MAX_OFFSET)) { 342 return 0; 343 } 344 #endif 345 346 image_block_spec.offset += nand_block_sz; 347 348 return 0; 349 } 350 351 static const struct plat_try_images_ops try_img_ops = { 352 .next_instance = try_nand_backup_partitions, 353 }; 354 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 355 356 #if STM32MP_RAW_NAND 357 static void boot_fmc2_nand(boot_api_context_t *boot_context) 358 { 359 int io_result __maybe_unused; 360 361 plat_setup_try_img_ops(&try_img_ops); 362 363 io_result = stm32_fmc2_init(); 364 assert(io_result == 0); 365 366 /* Register the IO device on this platform */ 367 io_result = register_io_dev_mtd(&nand_dev_con); 368 assert(io_result == 0); 369 370 /* Open connections to device */ 371 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 372 &storage_dev_handle); 373 assert(io_result == 0); 374 375 nand_block_sz = nand_dev_spec.erase_size; 376 } 377 #endif /* STM32MP_RAW_NAND */ 378 379 #if STM32MP_SPI_NAND 380 static void boot_spi_nand(boot_api_context_t *boot_context) 381 { 382 int io_result __maybe_unused; 383 384 plat_setup_try_img_ops(&try_img_ops); 385 386 io_result = stm32_qspi_init(); 387 assert(io_result == 0); 388 389 io_result = register_io_dev_mtd(&spi_dev_con); 390 assert(io_result == 0); 391 392 /* Open connections to device */ 393 io_result = io_dev_open(spi_dev_con, 394 (uintptr_t)&spi_nand_dev_spec, 395 &storage_dev_handle); 396 assert(io_result == 0); 397 398 nand_block_sz = spi_nand_dev_spec.erase_size; 399 } 400 #endif /* STM32MP_SPI_NAND */ 401 402 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 403 static void mmap_io_setup(void) 404 { 405 int io_result __maybe_unused; 406 407 io_result = register_io_dev_memmap(&memmap_dev_con); 408 assert(io_result == 0); 409 410 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, 411 &storage_dev_handle); 412 assert(io_result == 0); 413 } 414 415 #if STM32MP_UART_PROGRAMMER 416 static void stm32cubeprogrammer_uart(void) 417 { 418 int ret __maybe_unused; 419 boot_api_context_t *boot_context = 420 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 421 uintptr_t uart_base; 422 423 uart_base = get_uart_address(boot_context->boot_interface_instance); 424 ret = stm32cubeprog_uart_load(uart_base, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 425 assert(ret == 0); 426 } 427 #endif 428 429 #if STM32MP_USB_PROGRAMMER 430 static void stm32cubeprogrammer_usb(void) 431 { 432 int ret __maybe_unused; 433 struct usb_handle *pdev; 434 435 /* Init USB on platform */ 436 pdev = usb_dfu_plat_init(); 437 438 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 439 assert(ret == 0); 440 } 441 #endif 442 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 443 444 void stm32mp_io_setup(void) 445 { 446 int io_result __maybe_unused; 447 boot_api_context_t *boot_context = 448 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 449 450 print_boot_device(boot_context); 451 452 if ((boot_context->boot_partition_used_toboot == 1U) || 453 (boot_context->boot_partition_used_toboot == 2U)) { 454 INFO("Boot used partition fsbl%u\n", 455 boot_context->boot_partition_used_toboot); 456 } 457 458 io_result = register_io_dev_fip(&fip_dev_con); 459 assert(io_result == 0); 460 461 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 462 &fip_dev_handle); 463 464 #ifndef DECRYPTION_SUPPORT_none 465 io_result = register_io_dev_enc(&enc_dev_con); 466 assert(io_result == 0); 467 468 io_result = io_dev_open(enc_dev_con, (uintptr_t)NULL, 469 &enc_dev_handle); 470 assert(io_result == 0); 471 #endif 472 473 switch (boot_context->boot_interface_selected) { 474 #if STM32MP_SDMMC 475 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 476 dmbsy(); 477 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 478 break; 479 #endif 480 #if STM32MP_EMMC 481 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 482 dmbsy(); 483 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 484 break; 485 #endif 486 #if STM32MP_SPI_NOR 487 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 488 dmbsy(); 489 boot_spi_nor(boot_context); 490 break; 491 #endif 492 #if STM32MP_RAW_NAND 493 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 494 dmbsy(); 495 boot_fmc2_nand(boot_context); 496 break; 497 #endif 498 #if STM32MP_SPI_NAND 499 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 500 dmbsy(); 501 boot_spi_nand(boot_context); 502 break; 503 #endif 504 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 505 #if STM32MP_UART_PROGRAMMER 506 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 507 #endif 508 #if STM32MP_USB_PROGRAMMER 509 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 510 #endif 511 dmbsy(); 512 mmap_io_setup(); 513 break; 514 #endif 515 516 default: 517 ERROR("Boot interface %d not supported\n", 518 boot_context->boot_interface_selected); 519 panic(); 520 break; 521 } 522 } 523 524 int bl2_plat_handle_pre_image_load(unsigned int image_id) 525 { 526 static bool gpt_init_done __maybe_unused; 527 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 528 529 switch (boot_itf) { 530 #if STM32MP_SDMMC || STM32MP_EMMC 531 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 532 #if STM32MP_EMMC_BOOT 533 if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) { 534 break; 535 } 536 #endif 537 /* fallthrough */ 538 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 539 if (!gpt_init_done) { 540 /* 541 * With FWU Multi Bank feature enabled, the selection of 542 * the image to boot will be done by fwu_init calling the 543 * platform hook, plat_fwu_set_images_source. 544 */ 545 #if !PSA_FWU_SUPPORT 546 const partition_entry_t *entry; 547 const struct efi_guid fip_guid = STM32MP_FIP_GUID; 548 549 partition_init(GPT_IMAGE_ID); 550 entry = get_partition_entry_by_type(&fip_guid); 551 if (entry == NULL) { 552 entry = get_partition_entry(FIP_IMAGE_NAME); 553 if (entry == NULL) { 554 ERROR("Could NOT find the %s partition!\n", 555 FIP_IMAGE_NAME); 556 557 return -ENOENT; 558 } 559 } 560 561 image_block_spec.offset = entry->start; 562 image_block_spec.length = entry->length; 563 #endif 564 gpt_init_done = true; 565 } else { 566 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 567 568 assert(bl_mem_params != NULL); 569 570 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 571 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 572 } 573 574 break; 575 #endif 576 577 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 578 #if STM32MP_RAW_NAND 579 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 580 #endif 581 #if STM32MP_SPI_NAND 582 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 583 #endif 584 /* 585 * With FWU Multi Bank feature enabled, the selection of 586 * the image to boot will be done by fwu_init calling the 587 * platform hook, plat_fwu_set_images_source. 588 */ 589 #if !PSA_FWU_SUPPORT 590 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 591 #endif 592 break; 593 #endif 594 595 #if STM32MP_SPI_NOR 596 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 597 /* 598 * With FWU Multi Bank feature enabled, the selection of 599 * the image to boot will be done by fwu_init calling the 600 * platform hook, plat_fwu_set_images_source. 601 */ 602 #if !PSA_FWU_SUPPORT 603 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 604 #endif 605 break; 606 #endif 607 608 #if STM32MP_UART_PROGRAMMER 609 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 610 if (image_id == FW_CONFIG_ID) { 611 stm32cubeprogrammer_uart(); 612 /* FIP loaded at DWL address */ 613 image_block_spec.offset = DWL_BUFFER_BASE; 614 image_block_spec.length = DWL_BUFFER_SIZE; 615 } 616 break; 617 #endif 618 #if STM32MP_USB_PROGRAMMER 619 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 620 if (image_id == FW_CONFIG_ID) { 621 stm32cubeprogrammer_usb(); 622 /* FIP loaded at DWL address */ 623 image_block_spec.offset = DWL_BUFFER_BASE; 624 image_block_spec.length = DWL_BUFFER_SIZE; 625 } 626 break; 627 #endif 628 629 default: 630 ERROR("FIP Not found\n"); 631 panic(); 632 } 633 634 return 0; 635 } 636 637 /* 638 * Return an IO device handle and specification which can be used to access 639 * an image. Use this to enforce platform load policy. 640 */ 641 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 642 uintptr_t *image_spec) 643 { 644 int rc; 645 const struct plat_io_policy *policy; 646 647 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id); 648 rc = policy->check(policy->image_spec); 649 if (rc == 0) { 650 *image_spec = policy->image_spec; 651 *dev_handle = *(policy->dev_handle); 652 } 653 654 return rc; 655 } 656 657 #if PSA_FWU_SUPPORT 658 /* 659 * In each boot in non-trial mode, we set the BKP register to 660 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata. 661 * 662 * As long as the update agent didn't update the "accepted" field in metadata 663 * (i.e. we are in trial mode), we select the new active_index. 664 * To avoid infinite boot loop at trial boot we decrement a BKP register. 665 * If this counter is 0: 666 * - an unexpected TAMPER event raised (that resets the BKP registers to 0) 667 * - a power-off occurs before the update agent was able to update the 668 * "accepted' field 669 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode. 670 * we select the previous_active_index. 671 */ 672 uint32_t plat_fwu_get_boot_idx(void) 673 { 674 /* 675 * Select boot index and update boot counter only once per boot 676 * even if this function is called several times. 677 */ 678 static uint32_t boot_idx = INVALID_BOOT_IDX; 679 680 if (boot_idx == INVALID_BOOT_IDX) { 681 const struct fwu_metadata *data = fwu_get_metadata(); 682 683 boot_idx = data->active_index; 684 685 if (data->bank_state[boot_idx] == FWU_BANK_STATE_VALID) { 686 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) { 687 WARN("Trial FWU fails %u times\n", 688 FWU_MAX_TRIAL_REBOOT); 689 boot_idx = fwu_get_alternate_boot_bank(); 690 } 691 } else if (data->bank_state[boot_idx] == 692 FWU_BANK_STATE_ACCEPTED) { 693 stm32_set_max_fwu_trial_boot_cnt(); 694 } else { 695 ERROR("The active bank(%u) of the platform is in Invalid State.\n", 696 boot_idx); 697 boot_idx = fwu_get_alternate_boot_bank(); 698 stm32_clear_fwu_trial_boot_cnt(); 699 } 700 } 701 702 return boot_idx; 703 } 704 705 static void *stm32_get_image_spec(const struct efi_guid *img_type_guid) 706 { 707 unsigned int i; 708 709 for (i = 0U; i < MAX_NUMBER_IDS; i++) { 710 if ((guidcmp(&policies[i].img_type_guid, img_type_guid)) == 0) { 711 return (void *)policies[i].image_spec; 712 } 713 } 714 715 return NULL; 716 } 717 718 void plat_fwu_set_images_source(const struct fwu_metadata *metadata) 719 { 720 unsigned int i; 721 uint32_t boot_idx; 722 const partition_entry_t *entry __maybe_unused; 723 const struct fwu_image_entry *img_entry; 724 const void *img_type_guid; 725 const void *img_guid; 726 io_block_spec_t *image_spec; 727 const uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 728 729 boot_idx = plat_fwu_get_boot_idx(); 730 assert(boot_idx < NR_OF_FW_BANKS); 731 VERBOSE("Selecting to boot from bank %u\n", boot_idx); 732 733 img_entry = (void *)&metadata->fw_desc.img_entry; 734 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) { 735 img_type_guid = &img_entry[i].img_type_guid; 736 737 img_guid = &img_entry[i].img_bank_info[boot_idx].img_guid; 738 739 image_spec = stm32_get_image_spec(img_type_guid); 740 if (image_spec == NULL) { 741 ERROR("Unable to get image spec for the image in the metadata\n"); 742 panic(); 743 } 744 745 switch (boot_itf) { 746 #if (STM32MP_SDMMC || STM32MP_EMMC) 747 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 748 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 749 entry = get_partition_entry_by_guid(img_guid); 750 if (entry == NULL) { 751 ERROR("No partition with the uuid mentioned in metadata\n"); 752 panic(); 753 } 754 755 image_spec->offset = entry->start; 756 image_spec->length = entry->length; 757 break; 758 #endif 759 #if STM32MP_SPI_NOR 760 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 761 if (guidcmp(img_guid, &STM32MP_NOR_FIP_A_GUID) == 0) { 762 image_spec->offset = STM32MP_NOR_FIP_A_OFFSET; 763 } else if (guidcmp(img_guid, &STM32MP_NOR_FIP_B_GUID) == 0) { 764 image_spec->offset = STM32MP_NOR_FIP_B_OFFSET; 765 } else { 766 ERROR("Invalid uuid mentioned in metadata\n"); 767 panic(); 768 } 769 break; 770 #endif 771 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) 772 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 773 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 774 if (guidcmp(img_guid, &STM32MP_NAND_FIP_A_GUID) == 0) { 775 image_spec->offset = STM32MP_NAND_FIP_A_OFFSET; 776 } else if (guidcmp(img_guid, &STM32MP_NAND_FIP_B_GUID) == 0) { 777 image_spec->offset = STM32MP_NAND_FIP_B_OFFSET; 778 } else { 779 ERROR("Invalid uuid mentioned in metadata\n"); 780 panic(); 781 } 782 break; 783 #endif 784 default: 785 panic(); 786 break; 787 } 788 } 789 } 790 791 static int set_metadata_image_source(unsigned int image_id, 792 uintptr_t *handle, 793 uintptr_t *image_spec) 794 { 795 struct plat_io_policy *policy; 796 io_block_spec_t *spec __maybe_unused; 797 const partition_entry_t *entry __maybe_unused; 798 const uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 799 800 policy = &policies[image_id]; 801 spec = (io_block_spec_t *)policy->image_spec; 802 803 switch (boot_itf) { 804 #if (STM32MP_SDMMC || STM32MP_EMMC) 805 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 806 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 807 partition_init(GPT_IMAGE_ID); 808 809 if (image_id == FWU_METADATA_IMAGE_ID) { 810 entry = get_partition_entry(METADATA_PART_1); 811 } else { 812 entry = get_partition_entry(METADATA_PART_2); 813 } 814 815 if (entry == NULL) { 816 ERROR("Unable to find a metadata partition\n"); 817 return -ENOENT; 818 } 819 820 spec->offset = entry->start; 821 spec->length = entry->length; 822 break; 823 #endif 824 825 #if STM32MP_SPI_NOR 826 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 827 if (image_id == FWU_METADATA_IMAGE_ID) { 828 spec->offset = STM32MP_NOR_METADATA1_OFFSET; 829 } else { 830 spec->offset = STM32MP_NOR_METADATA2_OFFSET; 831 } 832 833 spec->length = sizeof(struct fwu_metadata); 834 break; 835 #endif 836 837 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) 838 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 839 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 840 if (image_id == FWU_METADATA_IMAGE_ID) { 841 spec->offset = STM32MP_NAND_METADATA1_OFFSET; 842 } else { 843 spec->offset = STM32MP_NAND_METADATA2_OFFSET; 844 } 845 846 spec->length = sizeof(struct fwu_metadata); 847 break; 848 #endif 849 default: 850 panic(); 851 break; 852 } 853 854 *image_spec = policy->image_spec; 855 *handle = *policy->dev_handle; 856 857 return 0; 858 } 859 860 int plat_fwu_set_metadata_image_source(unsigned int image_id, 861 uintptr_t *handle, 862 uintptr_t *image_spec) 863 { 864 assert((image_id == FWU_METADATA_IMAGE_ID) || 865 (image_id == BKUP_FWU_METADATA_IMAGE_ID)); 866 867 return set_metadata_image_source(image_id, handle, image_spec); 868 } 869 #endif /* PSA_FWU_SUPPORT */ 870