1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/fwu/fwu.h> 14 #include <drivers/fwu/fwu_metadata.h> 15 #include <drivers/io/io_block.h> 16 #include <drivers/io/io_driver.h> 17 #include <drivers/io/io_fip.h> 18 #include <drivers/io/io_memmap.h> 19 #include <drivers/io/io_mtd.h> 20 #include <drivers/io/io_storage.h> 21 #include <drivers/mmc.h> 22 #include <drivers/partition/efi.h> 23 #include <drivers/partition/partition.h> 24 #include <drivers/raw_nand.h> 25 #include <drivers/spi_nand.h> 26 #include <drivers/spi_nor.h> 27 #include <drivers/st/io_mmc.h> 28 #include <drivers/st/stm32_fmc2_nand.h> 29 #include <drivers/st/stm32_qspi.h> 30 #include <drivers/st/stm32_sdmmc2.h> 31 #include <drivers/usb_device.h> 32 #include <lib/fconf/fconf.h> 33 #include <lib/mmio.h> 34 #include <lib/utils.h> 35 #include <plat/common/platform.h> 36 #include <tools_share/firmware_image_package.h> 37 38 #include <platform_def.h> 39 #include <stm32cubeprogrammer.h> 40 #include <stm32mp_fconf_getter.h> 41 #include <stm32mp_io_storage.h> 42 #include <usb_dfu.h> 43 44 /* IO devices */ 45 uintptr_t fip_dev_handle; 46 uintptr_t storage_dev_handle; 47 48 static const io_dev_connector_t *fip_dev_con; 49 50 #if STM32MP_SDMMC || STM32MP_EMMC 51 static struct mmc_device_info mmc_info; 52 53 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 54 55 static io_block_dev_spec_t mmc_block_dev_spec = { 56 /* It's used as temp buffer in block driver */ 57 .buffer = { 58 .offset = (size_t)&block_buffer, 59 .length = MMC_BLOCK_SIZE, 60 }, 61 .ops = { 62 .read = mmc_read_blocks, 63 .write = NULL, 64 }, 65 .block_size = MMC_BLOCK_SIZE, 66 }; 67 68 static const io_dev_connector_t *mmc_dev_con; 69 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 70 71 #if STM32MP_SPI_NOR 72 static io_mtd_dev_spec_t spi_nor_dev_spec = { 73 .ops = { 74 .init = spi_nor_init, 75 .read = spi_nor_read, 76 }, 77 }; 78 #endif 79 80 #if STM32MP_RAW_NAND 81 static io_mtd_dev_spec_t nand_dev_spec = { 82 .ops = { 83 .init = nand_raw_init, 84 .read = nand_read, 85 .seek = nand_seek_bb 86 }, 87 }; 88 89 static const io_dev_connector_t *nand_dev_con; 90 #endif 91 92 #if STM32MP_SPI_NAND 93 static io_mtd_dev_spec_t spi_nand_dev_spec = { 94 .ops = { 95 .init = spi_nand_init, 96 .read = nand_read, 97 .seek = nand_seek_bb 98 }, 99 }; 100 #endif 101 102 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 103 static const io_dev_connector_t *spi_dev_con; 104 #endif 105 106 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 107 static const io_dev_connector_t *memmap_dev_con; 108 #endif 109 110 io_block_spec_t image_block_spec = { 111 .offset = 0U, 112 .length = 0U, 113 }; 114 115 int open_fip(const uintptr_t spec) 116 { 117 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 118 } 119 120 int open_storage(const uintptr_t spec) 121 { 122 return io_dev_init(storage_dev_handle, 0); 123 } 124 125 static void print_boot_device(boot_api_context_t *boot_context) 126 { 127 switch (boot_context->boot_interface_selected) { 128 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 129 INFO("Using SDMMC\n"); 130 break; 131 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 132 INFO("Using EMMC\n"); 133 break; 134 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 135 INFO("Using QSPI NOR\n"); 136 break; 137 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 138 INFO("Using FMC NAND\n"); 139 break; 140 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 141 INFO("Using SPI NAND\n"); 142 break; 143 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 144 INFO("Using UART\n"); 145 break; 146 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 147 INFO("Using USB\n"); 148 break; 149 default: 150 ERROR("Boot interface %u not found\n", 151 boot_context->boot_interface_selected); 152 panic(); 153 break; 154 } 155 156 if (boot_context->boot_interface_instance != 0U) { 157 INFO(" Instance %d\n", boot_context->boot_interface_instance); 158 } 159 } 160 161 #if STM32MP_SDMMC || STM32MP_EMMC 162 static void boot_mmc(enum mmc_device_type mmc_dev_type, 163 uint16_t boot_interface_instance) 164 { 165 int io_result __unused; 166 struct stm32_sdmmc2_params params; 167 168 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 169 170 mmc_info.mmc_dev_type = mmc_dev_type; 171 172 switch (boot_interface_instance) { 173 case 1: 174 params.reg_base = STM32MP_SDMMC1_BASE; 175 break; 176 case 2: 177 params.reg_base = STM32MP_SDMMC2_BASE; 178 break; 179 case 3: 180 params.reg_base = STM32MP_SDMMC3_BASE; 181 break; 182 default: 183 WARN("SDMMC instance not found, using default\n"); 184 if (mmc_dev_type == MMC_IS_SD) { 185 params.reg_base = STM32MP_SDMMC1_BASE; 186 } else { 187 params.reg_base = STM32MP_SDMMC2_BASE; 188 } 189 break; 190 } 191 192 params.device_info = &mmc_info; 193 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 194 ERROR("SDMMC%u init failed\n", boot_interface_instance); 195 panic(); 196 } 197 198 /* Open MMC as a block device to read GPT table */ 199 io_result = register_io_dev_block(&mmc_dev_con); 200 if (io_result != 0) { 201 panic(); 202 } 203 204 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 205 &storage_dev_handle); 206 assert(io_result == 0); 207 } 208 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 209 210 #if STM32MP_SPI_NOR 211 static void boot_spi_nor(boot_api_context_t *boot_context) 212 { 213 int io_result __unused; 214 215 io_result = stm32_qspi_init(); 216 assert(io_result == 0); 217 218 io_result = register_io_dev_mtd(&spi_dev_con); 219 assert(io_result == 0); 220 221 /* Open connections to device */ 222 io_result = io_dev_open(spi_dev_con, 223 (uintptr_t)&spi_nor_dev_spec, 224 &storage_dev_handle); 225 assert(io_result == 0); 226 } 227 #endif /* STM32MP_SPI_NOR */ 228 229 #if STM32MP_RAW_NAND 230 static void boot_fmc2_nand(boot_api_context_t *boot_context) 231 { 232 int io_result __unused; 233 234 io_result = stm32_fmc2_init(); 235 assert(io_result == 0); 236 237 /* Register the IO device on this platform */ 238 io_result = register_io_dev_mtd(&nand_dev_con); 239 assert(io_result == 0); 240 241 /* Open connections to device */ 242 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 243 &storage_dev_handle); 244 assert(io_result == 0); 245 } 246 #endif /* STM32MP_RAW_NAND */ 247 248 #if STM32MP_SPI_NAND 249 static void boot_spi_nand(boot_api_context_t *boot_context) 250 { 251 int io_result __unused; 252 253 io_result = stm32_qspi_init(); 254 assert(io_result == 0); 255 256 io_result = register_io_dev_mtd(&spi_dev_con); 257 assert(io_result == 0); 258 259 /* Open connections to device */ 260 io_result = io_dev_open(spi_dev_con, 261 (uintptr_t)&spi_nand_dev_spec, 262 &storage_dev_handle); 263 assert(io_result == 0); 264 } 265 #endif /* STM32MP_SPI_NAND */ 266 267 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 268 static void mmap_io_setup(void) 269 { 270 int io_result __unused; 271 272 io_result = register_io_dev_memmap(&memmap_dev_con); 273 assert(io_result == 0); 274 275 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, 276 &storage_dev_handle); 277 assert(io_result == 0); 278 } 279 280 #if STM32MP_UART_PROGRAMMER 281 static void stm32cubeprogrammer_uart(void) 282 { 283 int ret __unused; 284 boot_api_context_t *boot_context = 285 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 286 uintptr_t uart_base; 287 288 uart_base = get_uart_address(boot_context->boot_interface_instance); 289 ret = stm32cubeprog_uart_load(uart_base, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 290 assert(ret == 0); 291 } 292 #endif 293 294 #if STM32MP_USB_PROGRAMMER 295 static void stm32cubeprogrammer_usb(void) 296 { 297 int ret __unused; 298 struct usb_handle *pdev; 299 300 /* Init USB on platform */ 301 pdev = usb_dfu_plat_init(); 302 303 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 304 assert(ret == 0); 305 } 306 #endif 307 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 308 309 310 void stm32mp_io_setup(void) 311 { 312 int io_result __unused; 313 boot_api_context_t *boot_context = 314 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 315 316 print_boot_device(boot_context); 317 318 if ((boot_context->boot_partition_used_toboot == 1U) || 319 (boot_context->boot_partition_used_toboot == 2U)) { 320 INFO("Boot used partition fsbl%u\n", 321 boot_context->boot_partition_used_toboot); 322 } 323 324 io_result = register_io_dev_fip(&fip_dev_con); 325 assert(io_result == 0); 326 327 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 328 &fip_dev_handle); 329 330 switch (boot_context->boot_interface_selected) { 331 #if STM32MP_SDMMC 332 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 333 dmbsy(); 334 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 335 break; 336 #endif 337 #if STM32MP_EMMC 338 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 339 dmbsy(); 340 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 341 break; 342 #endif 343 #if STM32MP_SPI_NOR 344 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 345 dmbsy(); 346 boot_spi_nor(boot_context); 347 break; 348 #endif 349 #if STM32MP_RAW_NAND 350 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 351 dmbsy(); 352 boot_fmc2_nand(boot_context); 353 break; 354 #endif 355 #if STM32MP_SPI_NAND 356 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 357 dmbsy(); 358 boot_spi_nand(boot_context); 359 break; 360 #endif 361 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 362 #if STM32MP_UART_PROGRAMMER 363 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 364 #endif 365 #if STM32MP_USB_PROGRAMMER 366 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 367 #endif 368 dmbsy(); 369 mmap_io_setup(); 370 break; 371 #endif 372 373 default: 374 ERROR("Boot interface %d not supported\n", 375 boot_context->boot_interface_selected); 376 panic(); 377 break; 378 } 379 } 380 381 int bl2_plat_handle_pre_image_load(unsigned int image_id) 382 { 383 static bool gpt_init_done __unused; 384 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 385 386 switch (boot_itf) { 387 #if STM32MP_SDMMC || STM32MP_EMMC 388 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 389 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 390 if (!gpt_init_done) { 391 /* 392 * With FWU Multi Bank feature enabled, the selection of 393 * the image to boot will be done by fwu_init calling the 394 * platform hook, plat_fwu_set_images_source. 395 */ 396 #if !PSA_FWU_SUPPORT 397 const partition_entry_t *entry; 398 399 partition_init(GPT_IMAGE_ID); 400 entry = get_partition_entry(FIP_IMAGE_NAME); 401 if (entry == NULL) { 402 ERROR("Could NOT find the %s partition!\n", 403 FIP_IMAGE_NAME); 404 return -ENOENT; 405 } 406 407 image_block_spec.offset = entry->start; 408 image_block_spec.length = entry->length; 409 #endif 410 gpt_init_done = true; 411 } else { 412 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 413 assert(bl_mem_params != NULL); 414 415 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 416 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 417 } 418 419 break; 420 #endif 421 422 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 423 #if STM32MP_RAW_NAND 424 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 425 #endif 426 #if STM32MP_SPI_NAND 427 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 428 #endif 429 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 430 break; 431 #endif 432 433 #if STM32MP_SPI_NOR 434 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 435 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 436 break; 437 #endif 438 439 #if STM32MP_UART_PROGRAMMER 440 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 441 if (image_id == FW_CONFIG_ID) { 442 stm32cubeprogrammer_uart(); 443 /* FIP loaded at DWL address */ 444 image_block_spec.offset = DWL_BUFFER_BASE; 445 image_block_spec.length = DWL_BUFFER_SIZE; 446 } 447 break; 448 #endif 449 #if STM32MP_USB_PROGRAMMER 450 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 451 if (image_id == FW_CONFIG_ID) { 452 stm32cubeprogrammer_usb(); 453 /* FIP loaded at DWL address */ 454 image_block_spec.offset = DWL_BUFFER_BASE; 455 image_block_spec.length = DWL_BUFFER_SIZE; 456 } 457 break; 458 #endif 459 460 default: 461 ERROR("FIP Not found\n"); 462 panic(); 463 } 464 465 return 0; 466 } 467 468 /* 469 * Return an IO device handle and specification which can be used to access 470 * an image. Use this to enforce platform load policy. 471 */ 472 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 473 uintptr_t *image_spec) 474 { 475 int rc; 476 const struct plat_io_policy *policy; 477 478 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id); 479 rc = policy->check(policy->image_spec); 480 if (rc == 0) { 481 *image_spec = policy->image_spec; 482 *dev_handle = *(policy->dev_handle); 483 } 484 485 return rc; 486 } 487 488 #if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT 489 /* 490 * In each boot in non-trial mode, we set the BKP register to 491 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata. 492 * 493 * As long as the update agent didn't update the "accepted" field in metadata 494 * (i.e. we are in trial mode), we select the new active_index. 495 * To avoid infinite boot loop at trial boot we decrement a BKP register. 496 * If this counter is 0: 497 * - an unexpected TAMPER event raised (that resets the BKP registers to 0) 498 * - a power-off occurs before the update agent was able to update the 499 * "accepted' field 500 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode. 501 * we select the previous_active_index. 502 */ 503 #define INVALID_BOOT_IDX 0xFFFFFFFF 504 505 uint32_t plat_fwu_get_boot_idx(void) 506 { 507 /* 508 * Select boot index and update boot counter only once per boot 509 * even if this function is called several times. 510 */ 511 static uint32_t boot_idx = INVALID_BOOT_IDX; 512 const struct fwu_metadata *data; 513 514 data = fwu_get_metadata(); 515 516 if (boot_idx == INVALID_BOOT_IDX) { 517 boot_idx = data->active_index; 518 if (fwu_is_trial_run_state()) { 519 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) { 520 WARN("Trial FWU fails %u times\n", 521 FWU_MAX_TRIAL_REBOOT); 522 boot_idx = data->previous_active_index; 523 } 524 } else { 525 stm32_set_max_fwu_trial_boot_cnt(); 526 } 527 } 528 529 return boot_idx; 530 } 531 532 static void *stm32_get_image_spec(const uuid_t *img_type_uuid) 533 { 534 unsigned int i; 535 536 for (i = 0U; i < MAX_NUMBER_IDS; i++) { 537 if ((guidcmp(&policies[i].img_type_guid, img_type_uuid)) == 0) { 538 return (void *)policies[i].image_spec; 539 } 540 } 541 542 return NULL; 543 } 544 545 void plat_fwu_set_images_source(const struct fwu_metadata *metadata) 546 { 547 unsigned int i; 548 uint32_t boot_idx; 549 const partition_entry_t *entry; 550 const uuid_t *img_type_uuid, *img_uuid; 551 io_block_spec_t *image_spec; 552 553 boot_idx = plat_fwu_get_boot_idx(); 554 assert(boot_idx < NR_OF_FW_BANKS); 555 556 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) { 557 img_type_uuid = &metadata->img_entry[i].img_type_uuid; 558 image_spec = stm32_get_image_spec(img_type_uuid); 559 if (image_spec == NULL) { 560 ERROR("Unable to get image spec for the image in the metadata\n"); 561 panic(); 562 } 563 564 img_uuid = 565 &metadata->img_entry[i].img_props[boot_idx].img_uuid; 566 567 entry = get_partition_entry_by_uuid(img_uuid); 568 if (entry == NULL) { 569 ERROR("Unable to find the partition with the uuid mentioned in metadata\n"); 570 panic(); 571 } 572 573 image_spec->offset = entry->start; 574 image_spec->length = entry->length; 575 } 576 } 577 578 static int plat_set_image_source(unsigned int image_id, 579 uintptr_t *handle, 580 uintptr_t *image_spec, 581 const char *part_name) 582 { 583 struct plat_io_policy *policy; 584 io_block_spec_t *spec; 585 const partition_entry_t *entry = get_partition_entry(part_name); 586 587 if (entry == NULL) { 588 ERROR("Unable to find the %s partition\n", part_name); 589 return -ENOENT; 590 } 591 592 policy = &policies[image_id]; 593 594 spec = (io_block_spec_t *)policy->image_spec; 595 spec->offset = entry->start; 596 spec->length = entry->length; 597 598 *image_spec = policy->image_spec; 599 *handle = *policy->dev_handle; 600 601 return 0; 602 } 603 604 int plat_fwu_set_metadata_image_source(unsigned int image_id, 605 uintptr_t *handle, 606 uintptr_t *image_spec) 607 { 608 char *part_name; 609 610 assert((image_id == FWU_METADATA_IMAGE_ID) || 611 (image_id == BKUP_FWU_METADATA_IMAGE_ID)); 612 613 partition_init(GPT_IMAGE_ID); 614 615 if (image_id == FWU_METADATA_IMAGE_ID) { 616 part_name = METADATA_PART_1; 617 } else { 618 part_name = METADATA_PART_2; 619 } 620 621 return plat_set_image_source(image_id, handle, image_spec, 622 part_name); 623 } 624 #endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */ 625