1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/pl011.h> 16 #include <lib/mmio.h> 17 #include <sq_common.h> 18 19 static console_pl011_t console; 20 static entry_point_info_t bl32_image_ep_info; 21 static entry_point_info_t bl33_image_ep_info; 22 23 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); 24 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); 25 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA); 26 27 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 28 { 29 assert(sec_state_is_valid(type)); 30 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 31 } 32 33 /******************************************************************************* 34 * Gets SPSR for BL32 entry 35 ******************************************************************************/ 36 uint32_t sq_get_spsr_for_bl32_entry(void) 37 { 38 /* 39 * The Secure Payload Dispatcher service is responsible for 40 * setting the SPSR prior to entry into the BL32 image. 41 */ 42 return 0; 43 } 44 45 /******************************************************************************* 46 * Gets SPSR for BL33 entry 47 ******************************************************************************/ 48 uint32_t sq_get_spsr_for_bl33_entry(void) 49 { 50 unsigned long el_status; 51 unsigned int mode; 52 uint32_t spsr; 53 54 /* Figure out what mode we enter the non-secure world in */ 55 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 56 el_status &= ID_AA64PFR0_ELX_MASK; 57 58 mode = (el_status) ? MODE_EL2 : MODE_EL1; 59 60 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 61 return spsr; 62 } 63 64 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 65 u_register_t arg2, u_register_t arg3) 66 { 67 /* Initialize the console to provide early debug support */ 68 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 69 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 70 SQ_CONSOLE_BAUDRATE, &console); 71 72 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 73 CONSOLE_FLAG_RUNTIME); 74 75 /* There are no parameters from BL2 if BL31 is a reset vector */ 76 assert(arg0 == 0U); 77 assert(arg1 == 0U); 78 79 /* Initialize power controller before setting up topology */ 80 plat_sq_pwrc_setup(); 81 82 #ifdef SPD_opteed 83 struct draminfo di = {0}; 84 85 sq_scp_get_draminfo(&di); 86 87 /* 88 * Check if OP-TEE has been loaded in Secure RAM allocated 89 * from DRAM1 region 90 */ 91 if ((di.base1 + di.size1) <= BL32_BASE) { 92 NOTICE("OP-TEE has been loaded by SCP firmware\n"); 93 /* Populate entry point information for BL32 */ 94 SET_PARAM_HEAD(&bl32_image_ep_info, 95 PARAM_EP, 96 VERSION_1, 97 0); 98 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 99 bl32_image_ep_info.pc = BL32_BASE; 100 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 101 } else { 102 NOTICE("OP-TEE has not been loaded by SCP firmware\n"); 103 } 104 #endif /* SPD_opteed */ 105 106 /* Populate entry point information for BL33 */ 107 SET_PARAM_HEAD(&bl33_image_ep_info, 108 PARAM_EP, 109 VERSION_1, 110 0); 111 /* 112 * Tell BL31 where the non-trusted software image 113 * is located and the entry state information 114 */ 115 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 116 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 117 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 118 } 119 120 static void sq_configure_sys_timer(void) 121 { 122 unsigned int reg_val; 123 124 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 125 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 126 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 127 mmio_write_32(SQ_SYS_TIMCTL_BASE + 128 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 129 130 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 131 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 132 } 133 134 void bl31_platform_setup(void) 135 { 136 /* Initialize the CCN interconnect */ 137 plat_sq_interconnect_init(); 138 plat_sq_interconnect_enter_coherency(); 139 140 /* Initialize the GIC driver, cpu and distributor interfaces */ 141 sq_gic_driver_init(); 142 sq_gic_init(); 143 144 /* Enable and initialize the System level generic timer */ 145 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 146 CNTCR_FCREQ(0U) | CNTCR_EN); 147 148 /* Allow access to the System counter timer module */ 149 sq_configure_sys_timer(); 150 } 151 152 void bl31_plat_runtime_setup(void) 153 { 154 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 155 156 sq_scp_get_draminfo(di); 157 } 158 159 void bl31_plat_arch_setup(void) 160 { 161 static const mmap_region_t secure_partition_mmap[] = { 162 #if SPM_MM 163 MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, 164 PLAT_SPM_BUF_SIZE, 165 MT_RW_DATA | MT_SECURE), 166 MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE, 167 PLAT_SQ_SP_PRIV_SIZE, 168 MT_RW_DATA | MT_SECURE), 169 #endif 170 {0}, 171 }; 172 173 sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap); 174 enable_mmu_el3(XLAT_TABLE_NC); 175 176 #if SPM_MM 177 memcpy((void *)SPM_SHIM_EXCEPTIONS_START, 178 (void *)SPM_SHIM_EXCEPTIONS_LMA, 179 (uintptr_t)SPM_SHIM_EXCEPTIONS_END - 180 (uintptr_t)SPM_SHIM_EXCEPTIONS_START); 181 #endif 182 } 183 184 void bl31_plat_enable_mmu(uint32_t flags) 185 { 186 enable_mmu_el3(flags | XLAT_TABLE_NC); 187 } 188 189 unsigned int plat_get_syscnt_freq2(void) 190 { 191 unsigned int counter_base_frequency; 192 193 /* Read the frequency from Frequency modes table */ 194 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 195 196 /* The first entry of the frequency modes table must not be 0 */ 197 if (counter_base_frequency == 0) 198 panic(); 199 200 return counter_base_frequency; 201 } 202