1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <platform_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <pl011.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <sq_common.h> 16 17 static console_pl011_t console; 18 static entry_point_info_t bl32_image_ep_info; 19 static entry_point_info_t bl33_image_ep_info; 20 21 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 22 { 23 assert(sec_state_is_valid(type)); 24 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 25 } 26 27 /******************************************************************************* 28 * Gets SPSR for BL32 entry 29 ******************************************************************************/ 30 uint32_t sq_get_spsr_for_bl32_entry(void) 31 { 32 /* 33 * The Secure Payload Dispatcher service is responsible for 34 * setting the SPSR prior to entry into the BL32 image. 35 */ 36 return 0; 37 } 38 39 /******************************************************************************* 40 * Gets SPSR for BL33 entry 41 ******************************************************************************/ 42 uint32_t sq_get_spsr_for_bl33_entry(void) 43 { 44 unsigned long el_status; 45 unsigned int mode; 46 uint32_t spsr; 47 48 /* Figure out what mode we enter the non-secure world in */ 49 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 50 el_status &= ID_AA64PFR0_ELX_MASK; 51 52 mode = (el_status) ? MODE_EL2 : MODE_EL1; 53 54 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 55 return spsr; 56 } 57 58 void bl31_early_platform_setup(bl31_params_t *from_bl2, 59 void *plat_params_from_bl2) 60 { 61 /* Initialize the console to provide early debug support */ 62 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 63 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 64 SQ_CONSOLE_BAUDRATE, &console); 65 66 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 67 CONSOLE_FLAG_RUNTIME); 68 69 /* There are no parameters from BL2 if BL31 is a reset vector */ 70 assert(from_bl2 == NULL); 71 assert(plat_params_from_bl2 == NULL); 72 73 #ifdef BL32_BASE 74 /* Populate entry point information for BL32 */ 75 SET_PARAM_HEAD(&bl32_image_ep_info, 76 PARAM_EP, 77 VERSION_1, 78 0); 79 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 80 bl32_image_ep_info.pc = BL32_BASE; 81 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 82 #endif /* BL32_BASE */ 83 84 /* Populate entry point information for BL33 */ 85 SET_PARAM_HEAD(&bl33_image_ep_info, 86 PARAM_EP, 87 VERSION_1, 88 0); 89 /* 90 * Tell BL31 where the non-trusted software image 91 * is located and the entry state information 92 */ 93 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 94 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 95 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 96 } 97 98 static void sq_configure_sys_timer(void) 99 { 100 unsigned int reg_val; 101 102 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 103 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 104 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 105 mmio_write_32(SQ_SYS_TIMCTL_BASE + 106 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 107 108 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 109 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 110 } 111 112 void bl31_platform_setup(void) 113 { 114 /* Initialize the CCN interconnect */ 115 plat_sq_interconnect_init(); 116 plat_sq_interconnect_enter_coherency(); 117 118 /* Initialize the GIC driver, cpu and distributor interfaces */ 119 sq_gic_driver_init(); 120 sq_gic_init(); 121 122 /* Enable and initialize the System level generic timer */ 123 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 124 CNTCR_FCREQ(0) | CNTCR_EN); 125 126 /* Allow access to the System counter timer module */ 127 sq_configure_sys_timer(); 128 129 /* Initialize power controller before setting up topology */ 130 plat_sq_pwrc_setup(); 131 } 132 133 void bl31_plat_runtime_setup(void) 134 { 135 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 136 137 scpi_get_draminfo(di); 138 } 139 140 void bl31_plat_arch_setup(void) 141 { 142 sq_mmap_setup(BL31_BASE, BL31_SIZE, NULL); 143 enable_mmu_el3(XLAT_TABLE_NC); 144 } 145 146 void bl31_plat_enable_mmu(uint32_t flags) 147 { 148 enable_mmu_el3(flags | XLAT_TABLE_NC); 149 } 150 151 unsigned int plat_get_syscnt_freq2(void) 152 { 153 unsigned int counter_base_frequency; 154 155 /* Read the frequency from Frequency modes table */ 156 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 157 158 /* The first entry of the frequency modes table must not be 0 */ 159 if (counter_base_frequency == 0) 160 panic(); 161 162 return counter_base_frequency; 163 } 164