1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/pl011.h> 16 #include <lib/mmio.h> 17 #include <sq_common.h> 18 19 static console_t console; 20 static entry_point_info_t bl32_image_ep_info; 21 static entry_point_info_t bl33_image_ep_info; 22 23 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); 24 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); 25 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA); 26 27 unsigned int plat_get_syscnt_freq2(void) 28 { 29 unsigned int counter_base_frequency; 30 31 /* Read the frequency from Frequency modes table */ 32 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 33 34 /* The first entry of the frequency modes table must not be 0 */ 35 if (counter_base_frequency == 0) 36 panic(); 37 38 return counter_base_frequency; 39 } 40 41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 42 { 43 assert(sec_state_is_valid(type)); 44 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 45 } 46 47 /******************************************************************************* 48 * Gets SPSR for BL32 entry 49 ******************************************************************************/ 50 uint32_t sq_get_spsr_for_bl32_entry(void) 51 { 52 /* 53 * The Secure Payload Dispatcher service is responsible for 54 * setting the SPSR prior to entry into the BL32 image. 55 */ 56 return 0; 57 } 58 59 /******************************************************************************* 60 * Gets SPSR for BL33 entry 61 ******************************************************************************/ 62 uint32_t sq_get_spsr_for_bl33_entry(void) 63 { 64 unsigned long el_status; 65 unsigned int mode; 66 uint32_t spsr; 67 68 /* Figure out what mode we enter the non-secure world in */ 69 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 70 el_status &= ID_AA64PFR0_ELX_MASK; 71 72 mode = (el_status) ? MODE_EL2 : MODE_EL1; 73 74 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 75 return spsr; 76 } 77 78 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 79 u_register_t arg2, u_register_t arg3) 80 { 81 /* Initialize the console to provide early debug support */ 82 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 83 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 84 SQ_CONSOLE_BAUDRATE, &console); 85 86 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 87 88 /* There are no parameters from BL2 if BL31 is a reset vector */ 89 assert(arg0 == 0U); 90 assert(arg1 == 0U); 91 92 /* Initialize power controller before setting up topology */ 93 plat_sq_pwrc_setup(); 94 95 #ifdef SPD_opteed 96 struct draminfo di = {0}; 97 98 sq_scp_get_draminfo(&di); 99 100 /* 101 * Check if OP-TEE has been loaded in Secure RAM allocated 102 * from DRAM1 region 103 */ 104 if ((di.base1 + di.size1) <= BL32_BASE) { 105 NOTICE("OP-TEE has been loaded by SCP firmware\n"); 106 /* Populate entry point information for BL32 */ 107 SET_PARAM_HEAD(&bl32_image_ep_info, 108 PARAM_EP, 109 VERSION_1, 110 0); 111 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 112 bl32_image_ep_info.pc = BL32_BASE; 113 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 114 } else { 115 NOTICE("OP-TEE has not been loaded by SCP firmware\n"); 116 } 117 #endif /* SPD_opteed */ 118 119 /* Populate entry point information for BL33 */ 120 SET_PARAM_HEAD(&bl33_image_ep_info, 121 PARAM_EP, 122 VERSION_1, 123 0); 124 /* 125 * Tell BL31 where the non-trusted software image 126 * is located and the entry state information 127 */ 128 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 129 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 130 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 131 } 132 133 static void sq_configure_sys_timer(void) 134 { 135 unsigned int reg_val; 136 unsigned int freq_val = plat_get_syscnt_freq2(); 137 138 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 139 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 140 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 141 mmio_write_32(SQ_SYS_TIMCTL_BASE + 142 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 143 144 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 145 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 146 147 /* Initialize CNTFRQ register in CNTCTLBase frame */ 148 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 149 150 /* 151 * Initialize CNTFRQ register in Non-secure CNTBase frame. 152 * This is required for SynQuacer, because it does not 153 * follow ARM ARM in that the value updated in CNTFRQ is not 154 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. 155 */ 156 mmio_write_32(SQ_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); 157 } 158 159 void bl31_platform_setup(void) 160 { 161 /* Initialize the CCN interconnect */ 162 plat_sq_interconnect_init(); 163 plat_sq_interconnect_enter_coherency(); 164 165 /* Initialize the GIC driver, cpu and distributor interfaces */ 166 sq_gic_driver_init(); 167 sq_gic_init(); 168 169 /* Enable and initialize the System level generic timer */ 170 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 171 CNTCR_FCREQ(0U) | CNTCR_EN); 172 173 /* Allow access to the System counter timer module */ 174 sq_configure_sys_timer(); 175 } 176 177 void bl31_plat_runtime_setup(void) 178 { 179 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 180 181 sq_scp_get_draminfo(di); 182 } 183 184 void bl31_plat_arch_setup(void) 185 { 186 static const mmap_region_t secure_partition_mmap[] = { 187 #if SPM_MM 188 MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, 189 PLAT_SPM_BUF_SIZE, 190 MT_RW_DATA | MT_SECURE), 191 MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE, 192 PLAT_SQ_SP_PRIV_SIZE, 193 MT_RW_DATA | MT_SECURE), 194 #endif 195 {0}, 196 }; 197 198 sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap); 199 enable_mmu_el3(XLAT_TABLE_NC); 200 201 #if SPM_MM 202 memcpy((void *)SPM_SHIM_EXCEPTIONS_START, 203 (void *)SPM_SHIM_EXCEPTIONS_LMA, 204 (uintptr_t)SPM_SHIM_EXCEPTIONS_END - 205 (uintptr_t)SPM_SHIM_EXCEPTIONS_START); 206 #endif 207 } 208 209 void bl31_plat_enable_mmu(uint32_t flags) 210 { 211 enable_mmu_el3(flags | XLAT_TABLE_NC); 212 } 213