xref: /rk3399_ARM-atf/plat/socionext/synquacer/sq_bl31_setup.c (revision 5e5cfc21f0c70d8ea7a1bc2e6022d3cdbd4202af)
1c35d59a3SSumit Garg /*
2c35d59a3SSumit Garg  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3c35d59a3SSumit Garg  *
4c35d59a3SSumit Garg  * SPDX-License-Identifier: BSD-3-Clause
5c35d59a3SSumit Garg  */
6c35d59a3SSumit Garg 
7c35d59a3SSumit Garg #include <arch.h>
8c35d59a3SSumit Garg #include <arch_helpers.h>
9c35d59a3SSumit Garg #include <platform_def.h>
10c35d59a3SSumit Garg #include <assert.h>
11c35d59a3SSumit Garg #include <bl_common.h>
1267b40070SSumit Garg #include <pl011.h>
13c35d59a3SSumit Garg #include <debug.h>
14c35d59a3SSumit Garg 
1567b40070SSumit Garg static console_pl011_t console;
16*5e5cfc21SSumit Garg static entry_point_info_t bl32_image_ep_info;
17*5e5cfc21SSumit Garg static entry_point_info_t bl33_image_ep_info;
18*5e5cfc21SSumit Garg 
19*5e5cfc21SSumit Garg entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
20*5e5cfc21SSumit Garg {
21*5e5cfc21SSumit Garg 	assert(sec_state_is_valid(type));
22*5e5cfc21SSumit Garg 	return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
23*5e5cfc21SSumit Garg }
24*5e5cfc21SSumit Garg 
25*5e5cfc21SSumit Garg /*******************************************************************************
26*5e5cfc21SSumit Garg  * Gets SPSR for BL32 entry
27*5e5cfc21SSumit Garg  ******************************************************************************/
28*5e5cfc21SSumit Garg uint32_t sq_get_spsr_for_bl32_entry(void)
29*5e5cfc21SSumit Garg {
30*5e5cfc21SSumit Garg 	/*
31*5e5cfc21SSumit Garg 	 * The Secure Payload Dispatcher service is responsible for
32*5e5cfc21SSumit Garg 	 * setting the SPSR prior to entry into the BL32 image.
33*5e5cfc21SSumit Garg 	 */
34*5e5cfc21SSumit Garg 	return 0;
35*5e5cfc21SSumit Garg }
36*5e5cfc21SSumit Garg 
37*5e5cfc21SSumit Garg /*******************************************************************************
38*5e5cfc21SSumit Garg  * Gets SPSR for BL33 entry
39*5e5cfc21SSumit Garg  ******************************************************************************/
40*5e5cfc21SSumit Garg uint32_t sq_get_spsr_for_bl33_entry(void)
41*5e5cfc21SSumit Garg {
42*5e5cfc21SSumit Garg 	unsigned long el_status;
43*5e5cfc21SSumit Garg 	unsigned int mode;
44*5e5cfc21SSumit Garg 	uint32_t spsr;
45*5e5cfc21SSumit Garg 
46*5e5cfc21SSumit Garg 	/* Figure out what mode we enter the non-secure world in */
47*5e5cfc21SSumit Garg 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
48*5e5cfc21SSumit Garg 	el_status &= ID_AA64PFR0_ELX_MASK;
49*5e5cfc21SSumit Garg 
50*5e5cfc21SSumit Garg 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
51*5e5cfc21SSumit Garg 
52*5e5cfc21SSumit Garg 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
53*5e5cfc21SSumit Garg 	return spsr;
54*5e5cfc21SSumit Garg }
5567b40070SSumit Garg 
56c35d59a3SSumit Garg void bl31_early_platform_setup(bl31_params_t *from_bl2,
57c35d59a3SSumit Garg 				void *plat_params_from_bl2)
58c35d59a3SSumit Garg {
5967b40070SSumit Garg 	/* Initialize the console to provide early debug support */
6067b40070SSumit Garg 	(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
6167b40070SSumit Garg 			       PLAT_SQ_BOOT_UART_CLK_IN_HZ,
6267b40070SSumit Garg 			       SQ_CONSOLE_BAUDRATE, &console);
6367b40070SSumit Garg 
6467b40070SSumit Garg 	console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
6567b40070SSumit Garg 			  CONSOLE_FLAG_RUNTIME);
6667b40070SSumit Garg 
67c35d59a3SSumit Garg 	/* There are no parameters from BL2 if BL31 is a reset vector */
68c35d59a3SSumit Garg 	assert(from_bl2 == NULL);
69c35d59a3SSumit Garg 	assert(plat_params_from_bl2 == NULL);
70*5e5cfc21SSumit Garg 
71*5e5cfc21SSumit Garg #ifdef BL32_BASE
72*5e5cfc21SSumit Garg 	/* Populate entry point information for BL32 */
73*5e5cfc21SSumit Garg 	SET_PARAM_HEAD(&bl32_image_ep_info,
74*5e5cfc21SSumit Garg 				PARAM_EP,
75*5e5cfc21SSumit Garg 				VERSION_1,
76*5e5cfc21SSumit Garg 				0);
77*5e5cfc21SSumit Garg 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
78*5e5cfc21SSumit Garg 	bl32_image_ep_info.pc = BL32_BASE;
79*5e5cfc21SSumit Garg 	bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
80*5e5cfc21SSumit Garg #endif /* BL32_BASE */
81*5e5cfc21SSumit Garg 
82*5e5cfc21SSumit Garg 	/* Populate entry point information for BL33 */
83*5e5cfc21SSumit Garg 	SET_PARAM_HEAD(&bl33_image_ep_info,
84*5e5cfc21SSumit Garg 				PARAM_EP,
85*5e5cfc21SSumit Garg 				VERSION_1,
86*5e5cfc21SSumit Garg 				0);
87*5e5cfc21SSumit Garg 	/*
88*5e5cfc21SSumit Garg 	 * Tell BL31 where the non-trusted software image
89*5e5cfc21SSumit Garg 	 * is located and the entry state information
90*5e5cfc21SSumit Garg 	 */
91*5e5cfc21SSumit Garg 	bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
92*5e5cfc21SSumit Garg 	bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
93*5e5cfc21SSumit Garg 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
94c35d59a3SSumit Garg }
95c35d59a3SSumit Garg 
96c35d59a3SSumit Garg void bl31_platform_setup(void)
97c35d59a3SSumit Garg {
98c35d59a3SSumit Garg }
99c35d59a3SSumit Garg 
100c35d59a3SSumit Garg void bl31_plat_runtime_setup(void)
101c35d59a3SSumit Garg {
102c35d59a3SSumit Garg }
103c35d59a3SSumit Garg 
104c35d59a3SSumit Garg void bl31_plat_arch_setup(void)
105c35d59a3SSumit Garg {
106c35d59a3SSumit Garg }
107