xref: /rk3399_ARM-atf/plat/socionext/synquacer/sq_bl31_setup.c (revision 0eb275c9a2a78d30f3bc937a1ce59051dfa87c8d)
1c35d59a3SSumit Garg /*
2c35d59a3SSumit Garg  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3c35d59a3SSumit Garg  *
4c35d59a3SSumit Garg  * SPDX-License-Identifier: BSD-3-Clause
5c35d59a3SSumit Garg  */
6c35d59a3SSumit Garg 
7c35d59a3SSumit Garg #include <arch.h>
8c35d59a3SSumit Garg #include <arch_helpers.h>
9c35d59a3SSumit Garg #include <platform_def.h>
10c35d59a3SSumit Garg #include <assert.h>
11c35d59a3SSumit Garg #include <bl_common.h>
1267b40070SSumit Garg #include <pl011.h>
13c35d59a3SSumit Garg #include <debug.h>
14*0eb275c9SSumit Garg #include <sq_common.h>
15c35d59a3SSumit Garg 
1667b40070SSumit Garg static console_pl011_t console;
175e5cfc21SSumit Garg static entry_point_info_t bl32_image_ep_info;
185e5cfc21SSumit Garg static entry_point_info_t bl33_image_ep_info;
195e5cfc21SSumit Garg 
205e5cfc21SSumit Garg entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
215e5cfc21SSumit Garg {
225e5cfc21SSumit Garg 	assert(sec_state_is_valid(type));
235e5cfc21SSumit Garg 	return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
245e5cfc21SSumit Garg }
255e5cfc21SSumit Garg 
265e5cfc21SSumit Garg /*******************************************************************************
275e5cfc21SSumit Garg  * Gets SPSR for BL32 entry
285e5cfc21SSumit Garg  ******************************************************************************/
295e5cfc21SSumit Garg uint32_t sq_get_spsr_for_bl32_entry(void)
305e5cfc21SSumit Garg {
315e5cfc21SSumit Garg 	/*
325e5cfc21SSumit Garg 	 * The Secure Payload Dispatcher service is responsible for
335e5cfc21SSumit Garg 	 * setting the SPSR prior to entry into the BL32 image.
345e5cfc21SSumit Garg 	 */
355e5cfc21SSumit Garg 	return 0;
365e5cfc21SSumit Garg }
375e5cfc21SSumit Garg 
385e5cfc21SSumit Garg /*******************************************************************************
395e5cfc21SSumit Garg  * Gets SPSR for BL33 entry
405e5cfc21SSumit Garg  ******************************************************************************/
415e5cfc21SSumit Garg uint32_t sq_get_spsr_for_bl33_entry(void)
425e5cfc21SSumit Garg {
435e5cfc21SSumit Garg 	unsigned long el_status;
445e5cfc21SSumit Garg 	unsigned int mode;
455e5cfc21SSumit Garg 	uint32_t spsr;
465e5cfc21SSumit Garg 
475e5cfc21SSumit Garg 	/* Figure out what mode we enter the non-secure world in */
485e5cfc21SSumit Garg 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
495e5cfc21SSumit Garg 	el_status &= ID_AA64PFR0_ELX_MASK;
505e5cfc21SSumit Garg 
515e5cfc21SSumit Garg 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
525e5cfc21SSumit Garg 
535e5cfc21SSumit Garg 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
545e5cfc21SSumit Garg 	return spsr;
555e5cfc21SSumit Garg }
5667b40070SSumit Garg 
57c35d59a3SSumit Garg void bl31_early_platform_setup(bl31_params_t *from_bl2,
58c35d59a3SSumit Garg 				void *plat_params_from_bl2)
59c35d59a3SSumit Garg {
6067b40070SSumit Garg 	/* Initialize the console to provide early debug support */
6167b40070SSumit Garg 	(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
6267b40070SSumit Garg 			       PLAT_SQ_BOOT_UART_CLK_IN_HZ,
6367b40070SSumit Garg 			       SQ_CONSOLE_BAUDRATE, &console);
6467b40070SSumit Garg 
6567b40070SSumit Garg 	console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
6667b40070SSumit Garg 			  CONSOLE_FLAG_RUNTIME);
6767b40070SSumit Garg 
68c35d59a3SSumit Garg 	/* There are no parameters from BL2 if BL31 is a reset vector */
69c35d59a3SSumit Garg 	assert(from_bl2 == NULL);
70c35d59a3SSumit Garg 	assert(plat_params_from_bl2 == NULL);
715e5cfc21SSumit Garg 
725e5cfc21SSumit Garg #ifdef BL32_BASE
735e5cfc21SSumit Garg 	/* Populate entry point information for BL32 */
745e5cfc21SSumit Garg 	SET_PARAM_HEAD(&bl32_image_ep_info,
755e5cfc21SSumit Garg 				PARAM_EP,
765e5cfc21SSumit Garg 				VERSION_1,
775e5cfc21SSumit Garg 				0);
785e5cfc21SSumit Garg 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
795e5cfc21SSumit Garg 	bl32_image_ep_info.pc = BL32_BASE;
805e5cfc21SSumit Garg 	bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
815e5cfc21SSumit Garg #endif /* BL32_BASE */
825e5cfc21SSumit Garg 
835e5cfc21SSumit Garg 	/* Populate entry point information for BL33 */
845e5cfc21SSumit Garg 	SET_PARAM_HEAD(&bl33_image_ep_info,
855e5cfc21SSumit Garg 				PARAM_EP,
865e5cfc21SSumit Garg 				VERSION_1,
875e5cfc21SSumit Garg 				0);
885e5cfc21SSumit Garg 	/*
895e5cfc21SSumit Garg 	 * Tell BL31 where the non-trusted software image
905e5cfc21SSumit Garg 	 * is located and the entry state information
915e5cfc21SSumit Garg 	 */
925e5cfc21SSumit Garg 	bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
935e5cfc21SSumit Garg 	bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
945e5cfc21SSumit Garg 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
95c35d59a3SSumit Garg }
96c35d59a3SSumit Garg 
97c35d59a3SSumit Garg void bl31_platform_setup(void)
98c35d59a3SSumit Garg {
99*0eb275c9SSumit Garg 	/* Initialize the CCN interconnect */
100*0eb275c9SSumit Garg 	plat_sq_interconnect_init();
101*0eb275c9SSumit Garg 	plat_sq_interconnect_enter_coherency();
102c35d59a3SSumit Garg }
103c35d59a3SSumit Garg 
104c35d59a3SSumit Garg void bl31_plat_runtime_setup(void)
105c35d59a3SSumit Garg {
106c35d59a3SSumit Garg }
107c35d59a3SSumit Garg 
108c35d59a3SSumit Garg void bl31_plat_arch_setup(void)
109c35d59a3SSumit Garg {
110c35d59a3SSumit Garg }
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