1007a7a33SSumit Garg /* 2007a7a33SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3007a7a33SSumit Garg * 4007a7a33SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5007a7a33SSumit Garg */ 6007a7a33SSumit Garg 7007a7a33SSumit Garg #ifndef __SQ_COMMON_H__ 8007a7a33SSumit Garg #define __SQ_COMMON_H__ 9007a7a33SSumit Garg 10007a7a33SSumit Garg #include <sys/types.h> 118cd37d7bSSumit Garg #include <xlat_tables_v2.h> 12007a7a33SSumit Garg 13*cfe19f85SArd Biesheuvel struct draminfo { 14*cfe19f85SArd Biesheuvel uint32_t num_regions; 15*cfe19f85SArd Biesheuvel uint32_t reserved; 16*cfe19f85SArd Biesheuvel uint64_t base1; 17*cfe19f85SArd Biesheuvel uint64_t size1; 18*cfe19f85SArd Biesheuvel uint64_t base2; 19*cfe19f85SArd Biesheuvel uint64_t size2; 20*cfe19f85SArd Biesheuvel uint64_t base3; 21*cfe19f85SArd Biesheuvel uint64_t size3; 22*cfe19f85SArd Biesheuvel }; 23*cfe19f85SArd Biesheuvel 24*cfe19f85SArd Biesheuvel uint32_t scpi_get_draminfo(struct draminfo *info); 25*cfe19f85SArd Biesheuvel 2605377100SSumit Garg void plat_sq_pwrc_setup(void); 2705377100SSumit Garg 280eb275c9SSumit Garg void plat_sq_interconnect_init(void); 290eb275c9SSumit Garg void plat_sq_interconnect_enter_coherency(void); 300eb275c9SSumit Garg void plat_sq_interconnect_exit_coherency(void); 310eb275c9SSumit Garg 32007a7a33SSumit Garg unsigned int sq_calc_core_pos(u_register_t mpidr); 33007a7a33SSumit Garg 34b529799fSSumit Garg void sq_gic_driver_init(void); 35b529799fSSumit Garg void sq_gic_init(void); 36b529799fSSumit Garg void sq_gic_cpuif_enable(void); 37b529799fSSumit Garg void sq_gic_cpuif_disable(void); 38b529799fSSumit Garg void sq_gic_pcpu_init(void); 39b529799fSSumit Garg 408cd37d7bSSumit Garg void sq_mmap_setup(uintptr_t total_base, size_t total_size, 418cd37d7bSSumit Garg const struct mmap_region *mmap); 428cd37d7bSSumit Garg 43007a7a33SSumit Garg #endif /* __SQ_COMMON_H__ */ 44