1007a7a33SSumit Garg /* 2007a7a33SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3007a7a33SSumit Garg * 4007a7a33SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5007a7a33SSumit Garg */ 6007a7a33SSumit Garg 7c3cf06f1SAntonio Nino Diaz #ifndef SQ_COMMON_H 8c3cf06f1SAntonio Nino Diaz #define SQ_COMMON_H 9007a7a33SSumit Garg 1093c78ed2SAntonio Nino Diaz #include <stdint.h> 11*09d40e0eSAntonio Nino Diaz 12*09d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 13007a7a33SSumit Garg 14cfe19f85SArd Biesheuvel struct draminfo { 15cfe19f85SArd Biesheuvel uint32_t num_regions; 16cfe19f85SArd Biesheuvel uint32_t reserved; 17cfe19f85SArd Biesheuvel uint64_t base1; 18cfe19f85SArd Biesheuvel uint64_t size1; 19cfe19f85SArd Biesheuvel uint64_t base2; 20cfe19f85SArd Biesheuvel uint64_t size2; 21cfe19f85SArd Biesheuvel uint64_t base3; 22cfe19f85SArd Biesheuvel uint64_t size3; 23cfe19f85SArd Biesheuvel }; 24cfe19f85SArd Biesheuvel 25cfe19f85SArd Biesheuvel uint32_t scpi_get_draminfo(struct draminfo *info); 26cfe19f85SArd Biesheuvel 2705377100SSumit Garg void plat_sq_pwrc_setup(void); 2805377100SSumit Garg 290eb275c9SSumit Garg void plat_sq_interconnect_init(void); 300eb275c9SSumit Garg void plat_sq_interconnect_enter_coherency(void); 310eb275c9SSumit Garg void plat_sq_interconnect_exit_coherency(void); 320eb275c9SSumit Garg 33007a7a33SSumit Garg unsigned int sq_calc_core_pos(u_register_t mpidr); 34007a7a33SSumit Garg 35b529799fSSumit Garg void sq_gic_driver_init(void); 36b529799fSSumit Garg void sq_gic_init(void); 37b529799fSSumit Garg void sq_gic_cpuif_enable(void); 38b529799fSSumit Garg void sq_gic_cpuif_disable(void); 39b529799fSSumit Garg void sq_gic_pcpu_init(void); 40b529799fSSumit Garg 418cd37d7bSSumit Garg void sq_mmap_setup(uintptr_t total_base, size_t total_size, 428cd37d7bSSumit Garg const struct mmap_region *mmap); 438cd37d7bSSumit Garg 44c3cf06f1SAntonio Nino Diaz #endif /* SQ_COMMON_H */ 45