1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 /* Table of regions to map using the MMU. */ 41 const mmap_region_t plat_rk_mmap[] = { 42 MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(GPIO4_BASE, GPIO4_SIZE, 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 71 MT_DEVICE | MT_RW | MT_SECURE), 72 MAP_REGION_FLAT(SERVICE_NOC_0_BASE, NOC_0_SIZE, 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(SERVICE_NOC_1_BASE, NOC_1_SIZE, 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(SERVICE_NOC_2_BASE, NOC_2_SIZE, 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(SERVICE_NOC_3_BASE, NOC_3_SIZE, 79 MT_DEVICE | MT_RW | MT_SECURE), 80 81 { 0 } 82 }; 83 84 /* The RockChip power domain tree descriptor */ 85 const unsigned char rockchip_power_domain_tree_desc[] = { 86 /* No of root nodes */ 87 PLATFORM_SYSTEM_COUNT, 88 /* No of children for the root node */ 89 PLATFORM_CLUSTER_COUNT, 90 /* No of children for the first cluster node */ 91 PLATFORM_CLUSTER0_CORE_COUNT, 92 /* No of children for the second cluster node */ 93 PLATFORM_CLUSTER1_CORE_COUNT 94 }; 95 96 void secure_timer_init(void) 97 { 98 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 99 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 100 101 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 102 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 103 104 /* auto reload & enable the timer */ 105 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 106 TIMER_EN | TIMER_FMODE); 107 } 108 109 void sgrf_init(void) 110 { 111 /* security config for master */ 112 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 113 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 114 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 115 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 116 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 117 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 118 119 /* security config for slave */ 120 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 121 SGRF_PMU_SLV_S_CFGED | 122 SGRF_PMU_SLV_CRYPTO1_NS); 123 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 124 SGRF_PMU_SLV_CON1_CFG); 125 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 126 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 127 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 128 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 129 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 130 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 131 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 132 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 133 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 134 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 135 136 /* security config for ddr memery */ 137 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 138 SGRF_DDR_RGN_BYPS); 139 } 140 141 static void dma_secure_cfg(uint32_t secure) 142 { 143 if (secure) { 144 /* rgn0 secure for dmac0 and dmac1 */ 145 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 146 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 147 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 148 ); 149 150 /* set dmac0 boot, under secure state */ 151 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 152 SGRF_DMAC_CFG_S); 153 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 154 SGRF_DMAC_CFG_S); 155 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 156 SGRF_DMAC_CFG_S); 157 158 /* dmac0 soft reset */ 159 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 160 CRU_DMAC0_RST); 161 udelay(5); 162 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 163 CRU_DMAC0_RST_RLS); 164 165 /* set dmac1 boot, under secure state */ 166 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 167 SGRF_DMAC_CFG_S); 168 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 169 SGRF_DMAC_CFG_S); 170 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 171 SGRF_DMAC_CFG_S); 172 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 173 SGRF_DMAC_CFG_S); 174 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 175 SGRF_DMAC_CFG_S); 176 177 /* dmac1 soft reset */ 178 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 179 CRU_DMAC1_RST); 180 udelay(5); 181 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 182 CRU_DMAC1_RST_RLS); 183 } else { 184 /* rgn non-secure for dmac0 and dmac1 */ 185 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 186 DMAC1_RGN_NS | DMAC0_RGN_NS); 187 188 /* set dmac0 boot, under non-secure state */ 189 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 190 DMAC0_BOOT_CFG_NS); 191 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 192 DMAC0_BOOT_PERIPH_NS); 193 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 194 DMAC0_BOOT_ADDR_NS); 195 196 /* dmac0 soft reset */ 197 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 198 CRU_DMAC0_RST); 199 udelay(5); 200 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 201 CRU_DMAC0_RST_RLS); 202 203 /* set dmac1 boot, under non-secure state */ 204 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 205 DMAC1_BOOT_CFG_NS); 206 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 207 DMAC1_BOOT_PERIPH_L_NS); 208 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 209 DMAC1_BOOT_ADDR_NS); 210 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 211 DMAC1_BOOT_PERIPH_H_NS); 212 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 213 DMAC1_BOOT_IRQ_NS); 214 215 /* dmac1 soft reset */ 216 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 217 CRU_DMAC1_RST); 218 udelay(5); 219 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 220 CRU_DMAC1_RST_RLS); 221 } 222 } 223 224 /* pll suspend */ 225 struct deepsleep_data_s slp_data; 226 227 static void pll_suspend_prepare(uint32_t pll_id) 228 { 229 int i; 230 231 if (pll_id == PPLL_ID) 232 for (i = 0; i < PLL_CON_COUNT; i++) 233 slp_data.plls_con[pll_id][i] = 234 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 235 else 236 for (i = 0; i < PLL_CON_COUNT; i++) 237 slp_data.plls_con[pll_id][i] = 238 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 239 } 240 241 static void set_pll_slow_mode(uint32_t pll_id) 242 { 243 if (pll_id == PPLL_ID) 244 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 245 else 246 mmio_write_32((CRU_BASE + 247 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 248 } 249 250 static void set_pll_normal_mode(uint32_t pll_id) 251 { 252 if (pll_id == PPLL_ID) 253 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 254 else 255 mmio_write_32(CRU_BASE + 256 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 257 } 258 259 static void set_pll_bypass(uint32_t pll_id) 260 { 261 if (pll_id == PPLL_ID) 262 mmio_write_32(PMUCRU_BASE + 263 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 264 else 265 mmio_write_32(CRU_BASE + 266 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 267 } 268 269 static void _pll_suspend(uint32_t pll_id) 270 { 271 set_pll_slow_mode(pll_id); 272 set_pll_bypass(pll_id); 273 } 274 275 void plls_suspend(void) 276 { 277 uint32_t i, pll_id; 278 279 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 280 pll_suspend_prepare(pll_id); 281 282 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 283 slp_data.cru_clksel_con[i] = 284 mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); 285 286 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 287 slp_data.pmucru_clksel_con[i] = 288 mmio_read_32(PMUCRU_BASE + 289 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 290 291 _pll_suspend(CPLL_ID); 292 _pll_suspend(NPLL_ID); 293 _pll_suspend(VPLL_ID); 294 _pll_suspend(PPLL_ID); 295 _pll_suspend(GPLL_ID); 296 _pll_suspend(ABPLL_ID); 297 _pll_suspend(ALPLL_ID); 298 } 299 300 void clk_gate_con_save(void) 301 { 302 uint32_t i = 0; 303 304 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 305 slp_data.pmucru_gate_con[i] = 306 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); 307 308 for (i = 0; i < CRU_GATE_COUNT; i++) 309 slp_data.cru_gate_con[i] = 310 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); 311 } 312 313 void clk_gate_con_disable(void) 314 { 315 uint32_t i; 316 317 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 318 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); 319 320 for (i = 0; i < CRU_GATE_COUNT; i++) 321 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); 322 } 323 324 void clk_gate_con_restore(void) 325 { 326 uint32_t i; 327 328 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 329 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), 330 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); 331 332 for (i = 0; i < CRU_GATE_COUNT; i++) 333 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), 334 REG_SOC_WMSK | slp_data.cru_gate_con[i]); 335 } 336 337 static void set_plls_nobypass(uint32_t pll_id) 338 { 339 if (pll_id == PPLL_ID) 340 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 341 PLL_NO_BYPASS_MODE); 342 else 343 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 344 PLL_NO_BYPASS_MODE); 345 } 346 347 static void plls_resume_prepare(void) 348 { 349 int i; 350 351 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 352 mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), 353 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 354 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 355 mmio_write_32((PMUCRU_BASE + 356 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 357 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 358 } 359 360 void plls_resume(void) 361 { 362 int pll_id; 363 364 plls_resume_prepare(); 365 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) { 366 set_plls_nobypass(pll_id); 367 set_pll_normal_mode(pll_id); 368 } 369 } 370 371 void soc_global_soft_reset_init(void) 372 { 373 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 374 CRU_PMU_SGRF_RST_RLS); 375 376 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 377 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 378 } 379 380 void __dead2 soc_global_soft_reset(void) 381 { 382 set_pll_slow_mode(VPLL_ID); 383 set_pll_slow_mode(NPLL_ID); 384 set_pll_slow_mode(GPLL_ID); 385 set_pll_slow_mode(CPLL_ID); 386 set_pll_slow_mode(PPLL_ID); 387 set_pll_slow_mode(ABPLL_ID); 388 set_pll_slow_mode(ALPLL_ID); 389 390 dsb(); 391 392 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 393 394 /* 395 * Maybe the HW needs some times to reset the system, 396 * so we do not hope the core to excute valid codes. 397 */ 398 while (1) 399 ; 400 } 401 402 void plat_rockchip_soc_init(void) 403 { 404 secure_timer_init(); 405 dma_secure_cfg(0); 406 sgrf_init(); 407 soc_global_soft_reset_init(); 408 plat_rockchip_gpio_init(); 409 } 410