1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 /* Table of regions to map using the MMU. */ 41 const mmap_region_t plat_rk_mmap[] = { 42 MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 { 0 } 59 }; 60 61 /* The RockChip power domain tree descriptor */ 62 const unsigned char rockchip_power_domain_tree_desc[] = { 63 /* No of root nodes */ 64 PLATFORM_SYSTEM_COUNT, 65 /* No of children for the root node */ 66 PLATFORM_CLUSTER_COUNT, 67 /* No of children for the first cluster node */ 68 PLATFORM_CLUSTER0_CORE_COUNT, 69 /* No of children for the second cluster node */ 70 PLATFORM_CLUSTER1_CORE_COUNT 71 }; 72 73 void secure_timer_init(void) 74 { 75 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 76 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 77 78 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 79 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 80 81 /* auto reload & enable the timer */ 82 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 83 TIMER_EN | TIMER_FMODE); 84 } 85 86 void sgrf_init(void) 87 { 88 /* security config for master */ 89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 90 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 92 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 93 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 94 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 95 96 /* security config for slave */ 97 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 98 SGRF_PMU_SLV_S_CFGED | 99 SGRF_PMU_SLV_CRYPTO1_NS); 100 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 101 SGRF_PMU_SLV_CON1_CFG); 102 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 103 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 104 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 105 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 106 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 107 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 108 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 109 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 110 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 111 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 112 113 /* security config for ddr memery */ 114 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 115 SGRF_DDR_RGN_BYPS); 116 } 117 118 static void dma_secure_cfg(uint32_t secure) 119 { 120 if (secure) { 121 /* rgn0 secure for dmac0 and dmac1 */ 122 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 123 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 124 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 125 ); 126 127 /* set dmac0 boot, under secure state */ 128 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 129 SGRF_DMAC_CFG_S); 130 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 131 SGRF_DMAC_CFG_S); 132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 133 SGRF_DMAC_CFG_S); 134 135 /* dmac0 soft reset */ 136 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 137 CRU_DMAC0_RST); 138 udelay(5); 139 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 140 CRU_DMAC0_RST_RLS); 141 142 /* set dmac1 boot, under secure state */ 143 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 144 SGRF_DMAC_CFG_S); 145 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 146 SGRF_DMAC_CFG_S); 147 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 148 SGRF_DMAC_CFG_S); 149 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 150 SGRF_DMAC_CFG_S); 151 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 152 SGRF_DMAC_CFG_S); 153 154 /* dmac1 soft reset */ 155 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 156 CRU_DMAC1_RST); 157 udelay(5); 158 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 159 CRU_DMAC1_RST_RLS); 160 } else { 161 /* rgn non-secure for dmac0 and dmac1 */ 162 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 163 DMAC1_RGN_NS | DMAC0_RGN_NS); 164 165 /* set dmac0 boot, under non-secure state */ 166 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 167 DMAC0_BOOT_CFG_NS); 168 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 169 DMAC0_BOOT_PERIPH_NS); 170 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 171 DMAC0_BOOT_ADDR_NS); 172 173 /* dmac0 soft reset */ 174 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 175 CRU_DMAC0_RST); 176 udelay(5); 177 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 178 CRU_DMAC0_RST_RLS); 179 180 /* set dmac1 boot, under non-secure state */ 181 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 182 DMAC1_BOOT_CFG_NS); 183 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 184 DMAC1_BOOT_PERIPH_L_NS); 185 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 186 DMAC1_BOOT_ADDR_NS); 187 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 188 DMAC1_BOOT_PERIPH_H_NS); 189 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 190 DMAC1_BOOT_IRQ_NS); 191 192 /* dmac1 soft reset */ 193 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 194 CRU_DMAC1_RST); 195 udelay(5); 196 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 197 CRU_DMAC1_RST_RLS); 198 } 199 } 200 201 /* pll suspend */ 202 struct deepsleep_data_s slp_data; 203 204 static void pll_suspend_prepare(uint32_t pll_id) 205 { 206 int i; 207 208 if (pll_id == PPLL_ID) 209 for (i = 0; i < PLL_CON_COUNT; i++) 210 slp_data.plls_con[pll_id][i] = 211 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 212 else 213 for (i = 0; i < PLL_CON_COUNT; i++) 214 slp_data.plls_con[pll_id][i] = 215 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 216 } 217 218 static void set_pll_slow_mode(uint32_t pll_id) 219 { 220 if (pll_id == PPLL_ID) 221 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 222 else 223 mmio_write_32((CRU_BASE + 224 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 225 } 226 227 static void set_pll_normal_mode(uint32_t pll_id) 228 { 229 if (pll_id == PPLL_ID) 230 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 231 else 232 mmio_write_32(CRU_BASE + 233 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 234 } 235 236 static void set_pll_bypass(uint32_t pll_id) 237 { 238 if (pll_id == PPLL_ID) 239 mmio_write_32(PMUCRU_BASE + 240 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 241 else 242 mmio_write_32(CRU_BASE + 243 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 244 } 245 246 static void _pll_suspend(uint32_t pll_id) 247 { 248 set_pll_slow_mode(pll_id); 249 set_pll_bypass(pll_id); 250 } 251 252 void plls_suspend(void) 253 { 254 uint32_t i, pll_id; 255 256 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 257 pll_suspend_prepare(pll_id); 258 259 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 260 slp_data.cru_clksel_con[i] = 261 mmio_read_32(CRU_BASE + 262 CRU_CLKSEL_OFFSET + i * REG_SIZE); 263 264 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 265 slp_data.pmucru_clksel_con[i] = 266 mmio_read_32(PMUCRU_BASE + 267 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 268 269 _pll_suspend(CPLL_ID); 270 _pll_suspend(NPLL_ID); 271 _pll_suspend(VPLL_ID); 272 _pll_suspend(PPLL_ID); 273 _pll_suspend(GPLL_ID); 274 _pll_suspend(ABPLL_ID); 275 _pll_suspend(ALPLL_ID); 276 } 277 278 static void set_plls_nobypass(uint32_t pll_id) 279 { 280 if (pll_id == PPLL_ID) 281 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 282 PLL_NO_BYPASS_MODE); 283 else 284 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 285 PLL_NO_BYPASS_MODE); 286 } 287 288 static void plls_resume_prepare(void) 289 { 290 int i; 291 292 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 293 mmio_write_32((CRU_BASE + CRU_CLKSEL_OFFSET + i * REG_SIZE), 294 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 295 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 296 mmio_write_32((PMUCRU_BASE + 297 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 298 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 299 } 300 301 void plls_resume(void) 302 { 303 int pll_id; 304 305 plls_resume_prepare(); 306 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) { 307 set_plls_nobypass(pll_id); 308 set_pll_normal_mode(pll_id); 309 } 310 } 311 312 void soc_global_soft_reset_init(void) 313 { 314 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 315 CRU_PMU_SGRF_RST_RLS); 316 } 317 318 void __dead2 soc_global_soft_reset(void) 319 { 320 uint32_t temp_val; 321 322 set_pll_slow_mode(VPLL_ID); 323 set_pll_slow_mode(NPLL_ID); 324 set_pll_slow_mode(GPLL_ID); 325 set_pll_slow_mode(CPLL_ID); 326 set_pll_slow_mode(PPLL_ID); 327 set_pll_slow_mode(ABPLL_ID); 328 set_pll_slow_mode(ALPLL_ID); 329 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | 330 PMU_RST_BY_FIRST_SFT; 331 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); 332 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 333 334 /* 335 * Maybe the HW needs some times to reset the system, 336 * so we do not hope the core to excute valid codes. 337 */ 338 while (1) 339 ; 340 } 341 342 void plat_rockchip_soc_init(void) 343 { 344 secure_timer_init(); 345 dma_secure_cfg(0); 346 sgrf_init(); 347 soc_global_soft_reset_init(); 348 } 349