1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 /* Table of regions to map using the MMU. */ 41 const mmap_region_t plat_rk_mmap[] = { 42 MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 61 { 0 } 62 }; 63 64 /* The RockChip power domain tree descriptor */ 65 const unsigned char rockchip_power_domain_tree_desc[] = { 66 /* No of root nodes */ 67 PLATFORM_SYSTEM_COUNT, 68 /* No of children for the root node */ 69 PLATFORM_CLUSTER_COUNT, 70 /* No of children for the first cluster node */ 71 PLATFORM_CLUSTER0_CORE_COUNT, 72 /* No of children for the second cluster node */ 73 PLATFORM_CLUSTER1_CORE_COUNT 74 }; 75 76 void secure_timer_init(void) 77 { 78 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 79 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 80 81 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 82 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 83 84 /* auto reload & enable the timer */ 85 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 86 TIMER_EN | TIMER_FMODE); 87 } 88 89 void sgrf_init(void) 90 { 91 /* security config for master */ 92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 93 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 94 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 95 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 96 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 97 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 98 99 /* security config for slave */ 100 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 101 SGRF_PMU_SLV_S_CFGED | 102 SGRF_PMU_SLV_CRYPTO1_NS); 103 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 104 SGRF_PMU_SLV_CON1_CFG); 105 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 106 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 107 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 108 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 109 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 110 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 111 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 112 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 113 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 114 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 115 116 /* security config for ddr memery */ 117 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 118 SGRF_DDR_RGN_BYPS); 119 } 120 121 static void dma_secure_cfg(uint32_t secure) 122 { 123 if (secure) { 124 /* rgn0 secure for dmac0 and dmac1 */ 125 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 126 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 127 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 128 ); 129 130 /* set dmac0 boot, under secure state */ 131 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 132 SGRF_DMAC_CFG_S); 133 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 134 SGRF_DMAC_CFG_S); 135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 136 SGRF_DMAC_CFG_S); 137 138 /* dmac0 soft reset */ 139 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 140 CRU_DMAC0_RST); 141 udelay(5); 142 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 143 CRU_DMAC0_RST_RLS); 144 145 /* set dmac1 boot, under secure state */ 146 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 147 SGRF_DMAC_CFG_S); 148 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 149 SGRF_DMAC_CFG_S); 150 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 151 SGRF_DMAC_CFG_S); 152 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 153 SGRF_DMAC_CFG_S); 154 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 155 SGRF_DMAC_CFG_S); 156 157 /* dmac1 soft reset */ 158 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 159 CRU_DMAC1_RST); 160 udelay(5); 161 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 162 CRU_DMAC1_RST_RLS); 163 } else { 164 /* rgn non-secure for dmac0 and dmac1 */ 165 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 166 DMAC1_RGN_NS | DMAC0_RGN_NS); 167 168 /* set dmac0 boot, under non-secure state */ 169 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 170 DMAC0_BOOT_CFG_NS); 171 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 172 DMAC0_BOOT_PERIPH_NS); 173 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 174 DMAC0_BOOT_ADDR_NS); 175 176 /* dmac0 soft reset */ 177 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 178 CRU_DMAC0_RST); 179 udelay(5); 180 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 181 CRU_DMAC0_RST_RLS); 182 183 /* set dmac1 boot, under non-secure state */ 184 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 185 DMAC1_BOOT_CFG_NS); 186 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 187 DMAC1_BOOT_PERIPH_L_NS); 188 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 189 DMAC1_BOOT_ADDR_NS); 190 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 191 DMAC1_BOOT_PERIPH_H_NS); 192 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 193 DMAC1_BOOT_IRQ_NS); 194 195 /* dmac1 soft reset */ 196 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 197 CRU_DMAC1_RST); 198 udelay(5); 199 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 200 CRU_DMAC1_RST_RLS); 201 } 202 } 203 204 /* pll suspend */ 205 struct deepsleep_data_s slp_data; 206 207 static void pll_suspend_prepare(uint32_t pll_id) 208 { 209 int i; 210 211 if (pll_id == PPLL_ID) 212 for (i = 0; i < PLL_CON_COUNT; i++) 213 slp_data.plls_con[pll_id][i] = 214 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 215 else 216 for (i = 0; i < PLL_CON_COUNT; i++) 217 slp_data.plls_con[pll_id][i] = 218 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 219 } 220 221 static void set_pll_slow_mode(uint32_t pll_id) 222 { 223 if (pll_id == PPLL_ID) 224 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 225 else 226 mmio_write_32((CRU_BASE + 227 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 228 } 229 230 static void set_pll_normal_mode(uint32_t pll_id) 231 { 232 if (pll_id == PPLL_ID) 233 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 234 else 235 mmio_write_32(CRU_BASE + 236 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 237 } 238 239 static void set_pll_bypass(uint32_t pll_id) 240 { 241 if (pll_id == PPLL_ID) 242 mmio_write_32(PMUCRU_BASE + 243 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 244 else 245 mmio_write_32(CRU_BASE + 246 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 247 } 248 249 static void _pll_suspend(uint32_t pll_id) 250 { 251 set_pll_slow_mode(pll_id); 252 set_pll_bypass(pll_id); 253 } 254 255 void plls_suspend(void) 256 { 257 uint32_t i, pll_id; 258 259 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 260 pll_suspend_prepare(pll_id); 261 262 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 263 slp_data.cru_clksel_con[i] = 264 mmio_read_32(CRU_BASE + 265 CRU_CLKSEL_OFFSET + i * REG_SIZE); 266 267 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 268 slp_data.pmucru_clksel_con[i] = 269 mmio_read_32(PMUCRU_BASE + 270 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 271 272 _pll_suspend(CPLL_ID); 273 _pll_suspend(NPLL_ID); 274 _pll_suspend(VPLL_ID); 275 _pll_suspend(PPLL_ID); 276 _pll_suspend(GPLL_ID); 277 _pll_suspend(ABPLL_ID); 278 _pll_suspend(ALPLL_ID); 279 } 280 281 static void set_plls_nobypass(uint32_t pll_id) 282 { 283 if (pll_id == PPLL_ID) 284 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 285 PLL_NO_BYPASS_MODE); 286 else 287 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 288 PLL_NO_BYPASS_MODE); 289 } 290 291 static void plls_resume_prepare(void) 292 { 293 int i; 294 295 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 296 mmio_write_32((CRU_BASE + CRU_CLKSEL_OFFSET + i * REG_SIZE), 297 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 298 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 299 mmio_write_32((PMUCRU_BASE + 300 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 301 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 302 } 303 304 void plls_resume(void) 305 { 306 int pll_id; 307 308 plls_resume_prepare(); 309 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) { 310 set_plls_nobypass(pll_id); 311 set_pll_normal_mode(pll_id); 312 } 313 } 314 315 void soc_global_soft_reset_init(void) 316 { 317 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 318 CRU_PMU_SGRF_RST_RLS); 319 320 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 321 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 322 } 323 324 void __dead2 soc_global_soft_reset(void) 325 { 326 set_pll_slow_mode(VPLL_ID); 327 set_pll_slow_mode(NPLL_ID); 328 set_pll_slow_mode(GPLL_ID); 329 set_pll_slow_mode(CPLL_ID); 330 set_pll_slow_mode(PPLL_ID); 331 set_pll_slow_mode(ABPLL_ID); 332 set_pll_slow_mode(ALPLL_ID); 333 334 dsb(); 335 336 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 337 338 /* 339 * Maybe the HW needs some times to reset the system, 340 * so we do not hope the core to excute valid codes. 341 */ 342 while (1) 343 ; 344 } 345 346 void plat_rockchip_soc_init(void) 347 { 348 secure_timer_init(); 349 dma_secure_cfg(0); 350 sgrf_init(); 351 soc_global_soft_reset_init(); 352 } 353