1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 /* Table of regions to map using the MMU. */ 41 const mmap_region_t plat_rk_mmap[] = { 42 MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(GPIO4_BASE, GPIO4_SIZE, 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 71 MT_DEVICE | MT_RW | MT_SECURE), 72 { 0 } 73 }; 74 75 /* The RockChip power domain tree descriptor */ 76 const unsigned char rockchip_power_domain_tree_desc[] = { 77 /* No of root nodes */ 78 PLATFORM_SYSTEM_COUNT, 79 /* No of children for the root node */ 80 PLATFORM_CLUSTER_COUNT, 81 /* No of children for the first cluster node */ 82 PLATFORM_CLUSTER0_CORE_COUNT, 83 /* No of children for the second cluster node */ 84 PLATFORM_CLUSTER1_CORE_COUNT 85 }; 86 87 void secure_timer_init(void) 88 { 89 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 90 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 91 92 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 93 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 94 95 /* auto reload & enable the timer */ 96 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 97 TIMER_EN | TIMER_FMODE); 98 } 99 100 void sgrf_init(void) 101 { 102 /* security config for master */ 103 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 104 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 105 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 106 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 107 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 108 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 109 110 /* security config for slave */ 111 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 112 SGRF_PMU_SLV_S_CFGED | 113 SGRF_PMU_SLV_CRYPTO1_NS); 114 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 115 SGRF_PMU_SLV_CON1_CFG); 116 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 117 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 118 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 119 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 120 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 121 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 122 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 123 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 124 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 125 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 126 127 /* security config for ddr memery */ 128 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 129 SGRF_DDR_RGN_BYPS); 130 } 131 132 static void dma_secure_cfg(uint32_t secure) 133 { 134 if (secure) { 135 /* rgn0 secure for dmac0 and dmac1 */ 136 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 137 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 138 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 139 ); 140 141 /* set dmac0 boot, under secure state */ 142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 143 SGRF_DMAC_CFG_S); 144 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 145 SGRF_DMAC_CFG_S); 146 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 147 SGRF_DMAC_CFG_S); 148 149 /* dmac0 soft reset */ 150 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 151 CRU_DMAC0_RST); 152 udelay(5); 153 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 154 CRU_DMAC0_RST_RLS); 155 156 /* set dmac1 boot, under secure state */ 157 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 158 SGRF_DMAC_CFG_S); 159 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 160 SGRF_DMAC_CFG_S); 161 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 162 SGRF_DMAC_CFG_S); 163 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 164 SGRF_DMAC_CFG_S); 165 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 166 SGRF_DMAC_CFG_S); 167 168 /* dmac1 soft reset */ 169 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 170 CRU_DMAC1_RST); 171 udelay(5); 172 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 173 CRU_DMAC1_RST_RLS); 174 } else { 175 /* rgn non-secure for dmac0 and dmac1 */ 176 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 177 DMAC1_RGN_NS | DMAC0_RGN_NS); 178 179 /* set dmac0 boot, under non-secure state */ 180 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 181 DMAC0_BOOT_CFG_NS); 182 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 183 DMAC0_BOOT_PERIPH_NS); 184 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 185 DMAC0_BOOT_ADDR_NS); 186 187 /* dmac0 soft reset */ 188 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 189 CRU_DMAC0_RST); 190 udelay(5); 191 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 192 CRU_DMAC0_RST_RLS); 193 194 /* set dmac1 boot, under non-secure state */ 195 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 196 DMAC1_BOOT_CFG_NS); 197 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 198 DMAC1_BOOT_PERIPH_L_NS); 199 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 200 DMAC1_BOOT_ADDR_NS); 201 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 202 DMAC1_BOOT_PERIPH_H_NS); 203 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 204 DMAC1_BOOT_IRQ_NS); 205 206 /* dmac1 soft reset */ 207 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 208 CRU_DMAC1_RST); 209 udelay(5); 210 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 211 CRU_DMAC1_RST_RLS); 212 } 213 } 214 215 /* pll suspend */ 216 struct deepsleep_data_s slp_data; 217 218 static void pll_suspend_prepare(uint32_t pll_id) 219 { 220 int i; 221 222 if (pll_id == PPLL_ID) 223 for (i = 0; i < PLL_CON_COUNT; i++) 224 slp_data.plls_con[pll_id][i] = 225 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 226 else 227 for (i = 0; i < PLL_CON_COUNT; i++) 228 slp_data.plls_con[pll_id][i] = 229 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 230 } 231 232 static void set_pll_slow_mode(uint32_t pll_id) 233 { 234 if (pll_id == PPLL_ID) 235 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 236 else 237 mmio_write_32((CRU_BASE + 238 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 239 } 240 241 static void set_pll_normal_mode(uint32_t pll_id) 242 { 243 if (pll_id == PPLL_ID) 244 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 245 else 246 mmio_write_32(CRU_BASE + 247 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 248 } 249 250 static void set_pll_bypass(uint32_t pll_id) 251 { 252 if (pll_id == PPLL_ID) 253 mmio_write_32(PMUCRU_BASE + 254 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 255 else 256 mmio_write_32(CRU_BASE + 257 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 258 } 259 260 static void _pll_suspend(uint32_t pll_id) 261 { 262 set_pll_slow_mode(pll_id); 263 set_pll_bypass(pll_id); 264 } 265 266 void plls_suspend(void) 267 { 268 uint32_t i, pll_id; 269 270 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 271 pll_suspend_prepare(pll_id); 272 273 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 274 slp_data.cru_clksel_con[i] = 275 mmio_read_32(CRU_BASE + 276 CRU_CLKSEL_OFFSET + i * REG_SIZE); 277 278 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 279 slp_data.pmucru_clksel_con[i] = 280 mmio_read_32(PMUCRU_BASE + 281 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 282 283 _pll_suspend(CPLL_ID); 284 _pll_suspend(NPLL_ID); 285 _pll_suspend(VPLL_ID); 286 _pll_suspend(PPLL_ID); 287 _pll_suspend(GPLL_ID); 288 _pll_suspend(ABPLL_ID); 289 _pll_suspend(ALPLL_ID); 290 } 291 292 static void set_plls_nobypass(uint32_t pll_id) 293 { 294 if (pll_id == PPLL_ID) 295 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 296 PLL_NO_BYPASS_MODE); 297 else 298 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 299 PLL_NO_BYPASS_MODE); 300 } 301 302 static void plls_resume_prepare(void) 303 { 304 int i; 305 306 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 307 mmio_write_32((CRU_BASE + CRU_CLKSEL_OFFSET + i * REG_SIZE), 308 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 309 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 310 mmio_write_32((PMUCRU_BASE + 311 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 312 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 313 } 314 315 void plls_resume(void) 316 { 317 int pll_id; 318 319 plls_resume_prepare(); 320 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) { 321 set_plls_nobypass(pll_id); 322 set_pll_normal_mode(pll_id); 323 } 324 } 325 326 void soc_global_soft_reset_init(void) 327 { 328 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 329 CRU_PMU_SGRF_RST_RLS); 330 331 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 332 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 333 } 334 335 void __dead2 soc_global_soft_reset(void) 336 { 337 set_pll_slow_mode(VPLL_ID); 338 set_pll_slow_mode(NPLL_ID); 339 set_pll_slow_mode(GPLL_ID); 340 set_pll_slow_mode(CPLL_ID); 341 set_pll_slow_mode(PPLL_ID); 342 set_pll_slow_mode(ABPLL_ID); 343 set_pll_slow_mode(ALPLL_ID); 344 345 dsb(); 346 347 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 348 349 /* 350 * Maybe the HW needs some times to reset the system, 351 * so we do not hope the core to excute valid codes. 352 */ 353 while (1) 354 ; 355 } 356 357 void plat_rockchip_soc_init(void) 358 { 359 secure_timer_init(); 360 dma_secure_cfg(0); 361 sgrf_init(); 362 soc_global_soft_reset_init(); 363 plat_rockchip_gpio_init(); 364 } 365