1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 /* Table of regions to map using the MMU. */ 41 const mmap_region_t plat_rk_mmap[] = { 42 MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 45 { 0 } 46 }; 47 48 /* The RockChip power domain tree descriptor */ 49 const unsigned char rockchip_power_domain_tree_desc[] = { 50 /* No of root nodes */ 51 PLATFORM_SYSTEM_COUNT, 52 /* No of children for the root node */ 53 PLATFORM_CLUSTER_COUNT, 54 /* No of children for the first cluster node */ 55 PLATFORM_CLUSTER0_CORE_COUNT, 56 /* No of children for the second cluster node */ 57 PLATFORM_CLUSTER1_CORE_COUNT 58 }; 59 60 void secure_timer_init(void) 61 { 62 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 63 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 64 65 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 66 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 67 68 /* auto reload & enable the timer */ 69 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 70 TIMER_EN | TIMER_FMODE); 71 } 72 73 void sgrf_init(void) 74 { 75 /* security config for master */ 76 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 77 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 79 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 81 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 82 83 /* security config for slave */ 84 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 85 SGRF_PMU_SLV_S_CFGED | 86 SGRF_PMU_SLV_CRYPTO1_NS); 87 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 88 SGRF_PMU_SLV_CON1_CFG); 89 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 90 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 91 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 92 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 93 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 94 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 95 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 96 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 97 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 98 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 99 100 /* security config for ddr memery */ 101 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 102 SGRF_DDR_RGN_BYPS); 103 } 104 105 static void dma_secure_cfg(uint32_t secure) 106 { 107 if (secure) { 108 /* rgn0 secure for dmac0 and dmac1 */ 109 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 110 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 111 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 112 ); 113 114 /* set dmac0 boot, under secure state */ 115 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 116 SGRF_DMAC_CFG_S); 117 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 118 SGRF_DMAC_CFG_S); 119 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 120 SGRF_DMAC_CFG_S); 121 122 /* dmac0 soft reset */ 123 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 124 CRU_DMAC0_RST); 125 udelay(5); 126 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 127 CRU_DMAC0_RST_RLS); 128 129 /* set dmac1 boot, under secure state */ 130 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 131 SGRF_DMAC_CFG_S); 132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 133 SGRF_DMAC_CFG_S); 134 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 135 SGRF_DMAC_CFG_S); 136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 137 SGRF_DMAC_CFG_S); 138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 139 SGRF_DMAC_CFG_S); 140 141 /* dmac1 soft reset */ 142 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 143 CRU_DMAC1_RST); 144 udelay(5); 145 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 146 CRU_DMAC1_RST_RLS); 147 } else { 148 /* rgn non-secure for dmac0 and dmac1 */ 149 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 150 DMAC1_RGN_NS | DMAC0_RGN_NS); 151 152 /* set dmac0 boot, under non-secure state */ 153 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 154 DMAC0_BOOT_CFG_NS); 155 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 156 DMAC0_BOOT_PERIPH_NS); 157 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 158 DMAC0_BOOT_ADDR_NS); 159 160 /* dmac0 soft reset */ 161 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 162 CRU_DMAC0_RST); 163 udelay(5); 164 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 165 CRU_DMAC0_RST_RLS); 166 167 /* set dmac1 boot, under non-secure state */ 168 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 169 DMAC1_BOOT_CFG_NS); 170 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 171 DMAC1_BOOT_PERIPH_L_NS); 172 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 173 DMAC1_BOOT_ADDR_NS); 174 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 175 DMAC1_BOOT_PERIPH_H_NS); 176 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 177 DMAC1_BOOT_IRQ_NS); 178 179 /* dmac1 soft reset */ 180 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 181 CRU_DMAC1_RST); 182 udelay(5); 183 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 184 CRU_DMAC1_RST_RLS); 185 } 186 } 187 188 /* pll suspend */ 189 struct deepsleep_data_s slp_data; 190 191 static void pll_suspend_prepare(uint32_t pll_id) 192 { 193 int i; 194 195 if (pll_id == PPLL_ID) 196 for (i = 0; i < PLL_CON_COUNT; i++) 197 slp_data.plls_con[pll_id][i] = 198 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 199 else 200 for (i = 0; i < PLL_CON_COUNT; i++) 201 slp_data.plls_con[pll_id][i] = 202 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 203 } 204 205 static void set_pll_slow_mode(uint32_t pll_id) 206 { 207 if (pll_id == PPLL_ID) 208 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 209 else 210 mmio_write_32((CRU_BASE + 211 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 212 } 213 214 static void set_pll_normal_mode(uint32_t pll_id) 215 { 216 if (pll_id == PPLL_ID) 217 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 218 else 219 mmio_write_32(CRU_BASE + 220 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 221 } 222 223 static void set_pll_bypass(uint32_t pll_id) 224 { 225 if (pll_id == PPLL_ID) 226 mmio_write_32(PMUCRU_BASE + 227 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 228 else 229 mmio_write_32(CRU_BASE + 230 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 231 } 232 233 static void _pll_suspend(uint32_t pll_id) 234 { 235 set_pll_slow_mode(pll_id); 236 set_pll_bypass(pll_id); 237 } 238 239 void plls_suspend(void) 240 { 241 uint32_t i, pll_id; 242 243 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 244 pll_suspend_prepare(pll_id); 245 246 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 247 slp_data.cru_clksel_con[i] = 248 mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); 249 250 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 251 slp_data.pmucru_clksel_con[i] = 252 mmio_read_32(PMUCRU_BASE + 253 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 254 255 _pll_suspend(CPLL_ID); 256 _pll_suspend(NPLL_ID); 257 _pll_suspend(VPLL_ID); 258 _pll_suspend(PPLL_ID); 259 _pll_suspend(GPLL_ID); 260 _pll_suspend(ABPLL_ID); 261 _pll_suspend(ALPLL_ID); 262 } 263 264 void clk_gate_con_save(void) 265 { 266 uint32_t i = 0; 267 268 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 269 slp_data.pmucru_gate_con[i] = 270 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); 271 272 for (i = 0; i < CRU_GATE_COUNT; i++) 273 slp_data.cru_gate_con[i] = 274 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); 275 } 276 277 void clk_gate_con_disable(void) 278 { 279 uint32_t i; 280 281 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 282 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); 283 284 for (i = 0; i < CRU_GATE_COUNT; i++) 285 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); 286 } 287 288 void clk_gate_con_restore(void) 289 { 290 uint32_t i; 291 292 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 293 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), 294 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); 295 296 for (i = 0; i < CRU_GATE_COUNT; i++) 297 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), 298 REG_SOC_WMSK | slp_data.cru_gate_con[i]); 299 } 300 301 static void set_plls_nobypass(uint32_t pll_id) 302 { 303 if (pll_id == PPLL_ID) 304 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 305 PLL_NO_BYPASS_MODE); 306 else 307 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 308 PLL_NO_BYPASS_MODE); 309 } 310 311 static void plls_resume_prepare(void) 312 { 313 int i; 314 315 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 316 mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), 317 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 318 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 319 mmio_write_32((PMUCRU_BASE + 320 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 321 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 322 } 323 324 void plls_resume(void) 325 { 326 int pll_id; 327 328 plls_resume_prepare(); 329 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) { 330 set_plls_nobypass(pll_id); 331 set_pll_normal_mode(pll_id); 332 } 333 } 334 335 void soc_global_soft_reset_init(void) 336 { 337 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 338 CRU_PMU_SGRF_RST_RLS); 339 340 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 341 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 342 } 343 344 void __dead2 soc_global_soft_reset(void) 345 { 346 set_pll_slow_mode(VPLL_ID); 347 set_pll_slow_mode(NPLL_ID); 348 set_pll_slow_mode(GPLL_ID); 349 set_pll_slow_mode(CPLL_ID); 350 set_pll_slow_mode(PPLL_ID); 351 set_pll_slow_mode(ABPLL_ID); 352 set_pll_slow_mode(ALPLL_ID); 353 354 dsb(); 355 356 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 357 358 /* 359 * Maybe the HW needs some times to reset the system, 360 * so we do not hope the core to excute valid codes. 361 */ 362 while (1) 363 ; 364 } 365 366 void plat_rockchip_soc_init(void) 367 { 368 secure_timer_init(); 369 dma_secure_cfg(0); 370 sgrf_init(); 371 soc_global_soft_reset_init(); 372 plat_rockchip_gpio_init(); 373 } 374