1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <m0_param.h> 32 #include "rk3399_mcu.h" 33 34 /* PMU */ 35 #define PMU_PWRDN_ST 0x18 36 #define PMU_BUS_IDLE_REQ 0x60 37 #define PMU_BUS_IDLE_ST 0x64 38 #define PMU_NOC_AUTO_ENA 0xd8 39 40 /* PMU_BUS_IDLE_REQ */ 41 #define IDLE_REQ_MSCH1 (1 << 19) 42 #define IDLE_REQ_MSCH0 (1 << 18) 43 44 /* #define PMU_BUS_IDLE_ST */ 45 #define IDLE_MSCH1 (1 << 19) 46 #define IDLE_MSCH0 (1 << 18) 47 48 #define PD_VOP_PWR_STAT (1 << 20) 49 50 /* CRU */ 51 #define CRU_DPLL_CON0 0x40 52 #define CRU_DPLL_CON1 0x44 53 #define CRU_DPLL_CON2 0x48 54 #define CRU_DPLL_CON3 0x4c 55 #define CRU_DPLL_CON4 0x50 56 #define CRU_DPLL_CON5 0x54 57 58 #define CRU_DPLL_CON2 0x48 59 #define CRU_DPLL_CON3 0x4c 60 #define CRU_CLKGATE10_CON 0x328 61 #define CRU_CLKGATE28_CON 0x370 62 63 /* CRU_CLKGATE10_CON */ 64 #define ACLK_VOP0_PRE_SRC_EN (1 << 8) 65 #define HCLK_VOP0_PRE_EN (1 << 9) 66 #define ACLK_VOP1_PRE_SRC_EN (1 << 10) 67 #define HCLK_VOP1_PRE_EN (1 << 11) 68 #define DCLK_VOP0_SRC_EN (1 << 12) 69 #define DCLK_VOP1_SRC_EN (1 << 13) 70 71 /* CRU_CLKGATE28_CON */ 72 #define HCLK_VOP0_EN (1 << 2) 73 #define ACLK_VOP0_EN (1 << 3) 74 #define HCLK_VOP1_EN (1 << 6) 75 #define ACLK_VOP1_EN (1 << 7) 76 77 /* CRU_PLL_CON3 */ 78 #define PLL_SLOW_MODE 0 79 #define PLL_NORMAL_MODE 1 80 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) 81 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) 82 83 /* PMU CRU */ 84 #define PMU_CRU_GATEDIS_CON0 0x130 85 86 /* VOP */ 87 #define VOP_SYS_CTRL 0x8 88 #define VOP_SYS_CTRL1 0xc 89 #define VOP_WIN0_CTRL0 0x30 90 #define VOP_INTR_CLEAR0 0x284 91 #define VOP_INTR_RAW_STATUS0 0x28c 92 93 /* VOP_SYS_CTRL */ 94 #define VOP_DMA_STOP_EN (1 << 21) 95 #define VOP_STANDBY_EN (1 << 22) 96 97 /* VOP_WIN0_CTRL0 */ 98 #define WB_ENABLE (1 << 0) 99 100 /* VOP_INTR_CLEAR0 */ 101 #define INT_CLR_DMA_FINISH (1 << 15) 102 #define INT_CLR_LINE_FLAG1 (1 << 4) 103 #define INT_CLR_LINE_FLAG0 (1 << 3) 104 105 /* VOP_INTR_RAW_STATUS0 */ 106 #define INT_RAW_STATUS_DMA_FINISH (1 << 15) 107 #define INT_RAW_STATUS_LINE_FLAG1 (1 << 4) 108 #define INT_RAW_STATUS_LINE_FLAG0 (1 << 3) 109 110 /* CIC */ 111 #define CIC_CTRL0 0 112 #define CIC_CTRL1 0x4 113 #define CIC_STATUS0 0x10 114 115 static inline int check_dma_status(uint32_t vop_addr, uint32_t *clr_dma_flag) 116 { 117 if (*clr_dma_flag) { 118 mmio_write_32(vop_addr + VOP_INTR_CLEAR0, 0x80008000); 119 *clr_dma_flag = 0; 120 } 121 122 if ((mmio_read_32(vop_addr + VOP_SYS_CTRL) & 123 (VOP_STANDBY_EN | VOP_DMA_STOP_EN)) || 124 !(mmio_read_32(vop_addr + VOP_WIN0_CTRL0) & WB_ENABLE) || 125 (mmio_read_32(vop_addr + VOP_INTR_RAW_STATUS0) & 126 INT_RAW_STATUS_DMA_FINISH)) 127 return 1; 128 129 return 0; 130 } 131 132 static int wait_vop_dma_finish(void) 133 { 134 uint32_t clr_dma_flag = 1; 135 uint32_t ret = 0; 136 137 stopwatch_init_usecs_expire(60000); 138 while (((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & 139 PD_VOP_PWR_STAT) == 0)) { 140 /* 141 * VOPL case: 142 * CRU_CLKGATE10_CON(bit10): ACLK_VOP1_PRE_SRC_EN 143 * CRU_CLKGATE10_CON(bit11): HCLK_VOP1_PRE_EN 144 * CRU_CLKGATE10_CON(bit13): DCLK_VOP1_SRC_EN 145 * CRU_CLKGATE28_CON(bit7): ACLK_VOP1_EN 146 * CRU_CLKGATE28_CON(bit6): HCLK_VOP1_EN 147 * 148 * VOPB case: 149 * CRU_CLKGATE10_CON(bit8): ACLK_VOP0_PRE_SRC_EN 150 * CRU_CLKGATE10_CON(bit9): HCLK_VOP0_PRE_EN 151 * CRU_CLKGATE10_CON(bit12): DCLK_VOP0_SRC_EN 152 * CRU_CLKGATE28_CON(bit3): ACLK_VOP0_EN 153 * CRU_CLKGATE28_CON(bit2): HCLK_VOP0_EN 154 */ 155 if (((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE10_CON) & 156 0x2c00) == 0) && 157 ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE28_CON) & 158 0xc0) == 0)) { 159 if (check_dma_status(VOP_LITE_BASE_ADDR, &clr_dma_flag)) 160 return; 161 } else if (((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE10_CON) & 162 0x1300) == 0) && 163 ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE28_CON) & 164 0x0c) == 0)) { 165 if (check_dma_status(VOP_BIG_BASE_ADDR, &clr_dma_flag)) 166 return; 167 } else { 168 /* No VOPs are enabled, so don't wait. */ 169 return; 170 } 171 172 if (stopwatch_expired()) { 173 ret = 1; 174 goto out; 175 } 176 } 177 178 out: 179 stopwatch_reset(); 180 return ret; 181 } 182 183 static void idle_port(void) 184 { 185 mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 186 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 187 IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); 188 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 189 (IDLE_MSCH1 | IDLE_MSCH0)) != (IDLE_MSCH1 | IDLE_MSCH0)) 190 continue; 191 } 192 193 static void deidle_port(void) 194 { 195 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 196 IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); 197 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 198 (IDLE_MSCH1 | IDLE_MSCH0)) 199 continue; 200 } 201 202 static void ddr_set_pll(void) 203 { 204 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 205 206 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 207 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON0, 208 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 209 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON1, 210 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 211 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 212 213 while ((mmio_read_32(CRU_BASE_ADDR + CRU_DPLL_CON2) & (1u << 31)) == 0) 214 continue; 215 216 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 217 } 218 219 void handle_dram(void) 220 { 221 wait_vop_dma_finish(); 222 223 idle_port(); 224 225 mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 226 (((0x3 << 4) | (1 << 2) | 1) << 16) | 227 (1 << 2) | 1 | 228 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 229 while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 2)) == 0) 230 continue; 231 232 ddr_set_pll(); 233 mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 0x20002); 234 while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 0)) == 0) 235 continue; 236 237 deidle_port(); 238 } 239