1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <debug.h> 31 #include <arch_helpers.h> 32 #include <platform_def.h> 33 #include <plat_private.h> 34 #include <dram.h> 35 #include <pmu_regs.h> 36 #include <rk3399_def.h> 37 #include <soc.h> 38 #include <suspend.h> 39 40 #define PMUGRF_OS_REG0 0x300 41 #define PMUGRF_OS_REG1 0x304 42 #define PMUGRF_OS_REG2 0x308 43 #define PMUGRF_OS_REG3 0x30c 44 45 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ 46 ((n) << (8 + (ch) * 4))) 47 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ 48 ((n) << (9 + (ch) * 4))) 49 50 #define FBDIV_ENC(n) ((n) << 16) 51 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) 52 #define POSTDIV2_ENC(n) ((n) << 12) 53 #define POSTDIV2_DEC(n) (((n) >> 12) & 0x7) 54 #define POSTDIV1_ENC(n) ((n) << 8) 55 #define POSTDIV1_DEC(n) (((n) >> 8) & 0x7) 56 #define REFDIV_ENC(n) (n) 57 #define REFDIV_DEC(n) ((n) & 0x3f) 58 59 /* PMU CRU */ 60 #define PMUCRU_RSTNHOLD_CON0 0x120 61 #define PMUCRU_RSTNHOLD_CON1 0x124 62 63 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7)) 64 #define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8)) 65 66 #define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000) 67 68 /* 69 * Copy @num registers from @src to @dst 70 */ 71 __sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num) 72 { 73 while (num--) { 74 mmio_write_32(dst, mmio_read_32(src)); 75 dst += sizeof(uint32_t); 76 src += sizeof(uint32_t); 77 } 78 } 79 80 static __sramfunc uint32_t sram_get_timer_value(void) 81 { 82 /* 83 * Generic delay timer implementation expects the timer to be a down 84 * counter. We apply bitwise NOT operator to the tick values returned 85 * by read_cntpct_el0() to simulate the down counter. 86 */ 87 return (uint32_t)(~read_cntpct_el0()); 88 } 89 90 static __sramfunc void sram_udelay(uint32_t usec) 91 { 92 uint32_t start, cnt, delta, delta_us; 93 94 /* counter is decreasing */ 95 start = sram_get_timer_value(); 96 do { 97 cnt = sram_get_timer_value(); 98 if (cnt > start) { 99 delta = UINT32_MAX - cnt; 100 delta += start; 101 } else 102 delta = start - cnt; 103 delta_us = (delta * SYS_COUNTER_FREQ_IN_MHZ); 104 } while (delta_us < usec); 105 } 106 107 static __sramfunc void configure_sgrf(void) 108 { 109 /* 110 * SGRF_DDR_RGN_DPLL_CLK and SGRF_DDR_RGN_RTC_CLK: 111 * IC ECO bug, need to set this register. 112 * 113 * SGRF_DDR_RGN_BYPS: 114 * After the PD_CENTER suspend/resume, the DDR region 115 * related registers in the SGRF will be reset, we 116 * need to re-initialize them. 117 */ 118 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 119 SGRF_DDR_RGN_DPLL_CLK | 120 SGRF_DDR_RGN_RTC_CLK | 121 SGRF_DDR_RGN_BYPS); 122 } 123 124 static __sramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, 125 uint32_t phy) 126 { 127 channel &= 0x1; 128 ctl &= 0x1; 129 phy &= 0x1; 130 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), 131 CRU_SFTRST_DDR_CTRL(channel, ctl) | 132 CRU_SFTRST_DDR_PHY(channel, phy)); 133 } 134 135 static __sramfunc void phy_pctrl_reset(uint32_t ch) 136 { 137 rkclk_ddr_reset(ch, 1, 1); 138 sram_udelay(10); 139 rkclk_ddr_reset(ch, 1, 0); 140 sram_udelay(10); 141 rkclk_ddr_reset(ch, 0, 0); 142 sram_udelay(10); 143 } 144 145 static __sramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t hz) 146 { 147 if (hz <= 125 * MHz) { 148 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 149 mmio_setbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8); 150 mmio_setbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8); 151 mmio_setbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8); 152 mmio_setbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8); 153 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 154 mmio_setbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16); 155 mmio_setbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16); 156 mmio_setbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16); 157 } else { 158 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 159 mmio_clrbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8); 160 mmio_clrbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8); 161 mmio_clrbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8); 162 mmio_clrbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8); 163 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 164 mmio_clrbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16); 165 mmio_clrbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16); 166 mmio_clrbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16); 167 } 168 } 169 170 static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) 171 { 172 /* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */ 173 mmio_clrsetbits_32(PHY_REG(ch, 8), 0x1 << 24, rank << 24); 174 mmio_clrsetbits_32(PHY_REG(ch, 136), 0x1 << 24, rank << 24); 175 mmio_clrsetbits_32(PHY_REG(ch, 264), 0x1 << 24, rank << 24); 176 mmio_clrsetbits_32(PHY_REG(ch, 392), 0x1 << 24, rank << 24); 177 } 178 179 static __sramfunc void select_per_cs_training_index(uint32_t ch, uint32_t rank) 180 { 181 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ 182 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) 183 set_cs_training_index(ch, rank); 184 } 185 186 static void override_write_leveling_value(uint32_t ch) 187 { 188 uint32_t byte; 189 190 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 191 mmio_setbits_32(PHY_REG(ch, 896), 1); 192 193 /* 194 * PHY_8/136/264/392 195 * phy_per_cs_training_multicast_en_X 1bit offset_16 196 */ 197 mmio_clrsetbits_32(PHY_REG(ch, 8), 0x1 << 16, 1 << 16); 198 mmio_clrsetbits_32(PHY_REG(ch, 136), 0x1 << 16, 1 << 16); 199 mmio_clrsetbits_32(PHY_REG(ch, 264), 0x1 << 16, 1 << 16); 200 mmio_clrsetbits_32(PHY_REG(ch, 392), 0x1 << 16, 1 << 16); 201 202 for (byte = 0; byte < 4; byte++) 203 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), 204 0xffff << 16, 205 0x200 << 16); 206 207 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 208 mmio_clrbits_32(PHY_REG(ch, 896), 1); 209 210 /* CTL_200 ctrlupd_req 1bit offset_8 */ 211 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); 212 } 213 214 static __sramfunc int data_training(uint32_t ch, 215 struct rk3399_sdram_params *sdram_params, 216 uint32_t training_flag) 217 { 218 uint32_t obs_0, obs_1, obs_2, obs_3, obs_err = 0; 219 uint32_t rank = sdram_params->ch[ch].rank; 220 uint32_t rank_mask; 221 uint32_t i, tmp; 222 223 if (sdram_params->dramtype == LPDDR4) 224 rank_mask = (rank == 1) ? 0x5 : 0xf; 225 else 226 rank_mask = (rank == 1) ? 0x1 : 0x3; 227 228 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 229 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); 230 231 if (training_flag == PI_FULL_TRAINING) { 232 if (sdram_params->dramtype == LPDDR4) { 233 training_flag = PI_WRITE_LEVELING | 234 PI_READ_GATE_TRAINING | 235 PI_READ_LEVELING | 236 PI_WDQ_LEVELING; 237 } else if (sdram_params->dramtype == LPDDR3) { 238 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 239 PI_READ_GATE_TRAINING; 240 } else if (sdram_params->dramtype == DDR3) { 241 training_flag = PI_WRITE_LEVELING | 242 PI_READ_GATE_TRAINING | 243 PI_READ_LEVELING; 244 } 245 } 246 247 /* ca training(LPDDR4,LPDDR3 support) */ 248 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { 249 for (i = 0; i < 4; i++) { 250 if (!(rank_mask & (1 << i))) 251 continue; 252 253 select_per_cs_training_index(ch, i); 254 /* PI_100 PI_CALVL_EN:RW:8:2 */ 255 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); 256 257 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ 258 mmio_clrsetbits_32(PI_REG(ch, 92), 259 (0x1 << 16) | (0x3 << 24), 260 (0x1 << 16) | (i << 24)); 261 while (1) { 262 /* PI_174 PI_INT_STATUS:RD:8:18 */ 263 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 264 265 /* 266 * check status obs 267 * PHY_532/660/788 phy_adr_calvl_obs1_:0:32 268 */ 269 obs_0 = mmio_read_32(PHY_REG(ch, 532)); 270 obs_1 = mmio_read_32(PHY_REG(ch, 660)); 271 obs_2 = mmio_read_32(PHY_REG(ch, 788)); 272 if (((obs_0 >> 30) & 0x3) || 273 ((obs_1 >> 30) & 0x3) || 274 ((obs_2 >> 30) & 0x3)) 275 obs_err = 1; 276 if ((((tmp >> 11) & 0x1) == 0x1) && 277 (((tmp >> 13) & 0x1) == 0x1) && 278 (((tmp >> 5) & 0x1) == 0x0) && 279 (obs_err == 0)) 280 break; 281 else if ((((tmp >> 5) & 0x1) == 0x1) || 282 (obs_err == 1)) 283 return -1; 284 } 285 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 286 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 287 } 288 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); 289 } 290 291 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ 292 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { 293 for (i = 0; i < rank; i++) { 294 select_per_cs_training_index(ch, i); 295 /* PI_60 PI_WRLVL_EN:RW:8:2 */ 296 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); 297 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ 298 mmio_clrsetbits_32(PI_REG(ch, 59), 299 (0x1 << 8) | (0x3 << 16), 300 (0x1 << 8) | (i << 16)); 301 302 while (1) { 303 /* PI_174 PI_INT_STATUS:RD:8:18 */ 304 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 305 306 /* 307 * check status obs, if error maybe can not 308 * get leveling done PHY_40/168/296/424 309 * phy_wrlvl_status_obs_X:0:13 310 */ 311 obs_0 = mmio_read_32(PHY_REG(ch, 40)); 312 obs_1 = mmio_read_32(PHY_REG(ch, 168)); 313 obs_2 = mmio_read_32(PHY_REG(ch, 296)); 314 obs_3 = mmio_read_32(PHY_REG(ch, 424)); 315 if (((obs_0 >> 12) & 0x1) || 316 ((obs_1 >> 12) & 0x1) || 317 ((obs_2 >> 12) & 0x1) || 318 ((obs_3 >> 12) & 0x1)) 319 obs_err = 1; 320 if ((((tmp >> 10) & 0x1) == 0x1) && 321 (((tmp >> 13) & 0x1) == 0x1) && 322 (((tmp >> 4) & 0x1) == 0x0) && 323 (obs_err == 0)) 324 break; 325 else if ((((tmp >> 4) & 0x1) == 0x1) || 326 (obs_err == 1)) 327 return -1; 328 } 329 330 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 331 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 332 } 333 override_write_leveling_value(ch); 334 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); 335 } 336 337 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ 338 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { 339 for (i = 0; i < rank; i++) { 340 select_per_cs_training_index(ch, i); 341 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ 342 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, 343 0x2 << 24); 344 /* 345 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 346 * PI_RDLVL_CS:RW:24:2 347 */ 348 mmio_clrsetbits_32(PI_REG(ch, 74), 349 (0x1 << 16) | (0x3 << 24), 350 (0x1 << 16) | (i << 24)); 351 352 while (1) { 353 /* PI_174 PI_INT_STATUS:RD:8:18 */ 354 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 355 356 /* 357 * check status obs 358 * PHY_43/171/299/427 359 * PHY_GTLVL_STATUS_OBS_x:16:8 360 */ 361 obs_0 = mmio_read_32(PHY_REG(ch, 43)); 362 obs_1 = mmio_read_32(PHY_REG(ch, 171)); 363 obs_2 = mmio_read_32(PHY_REG(ch, 299)); 364 obs_3 = mmio_read_32(PHY_REG(ch, 427)); 365 if (((obs_0 >> (16 + 6)) & 0x3) || 366 ((obs_1 >> (16 + 6)) & 0x3) || 367 ((obs_2 >> (16 + 6)) & 0x3) || 368 ((obs_3 >> (16 + 6)) & 0x3)) 369 obs_err = 1; 370 if ((((tmp >> 9) & 0x1) == 0x1) && 371 (((tmp >> 13) & 0x1) == 0x1) && 372 (((tmp >> 3) & 0x1) == 0x0) && 373 (obs_err == 0)) 374 break; 375 else if ((((tmp >> 3) & 0x1) == 0x1) || 376 (obs_err == 1)) 377 return -1; 378 } 379 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 380 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 381 } 382 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); 383 } 384 385 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ 386 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { 387 for (i = 0; i < rank; i++) { 388 select_per_cs_training_index(ch, i); 389 /* PI_80 PI_RDLVL_EN:RW:16:2 */ 390 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, 391 0x2 << 16); 392 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ 393 mmio_clrsetbits_32(PI_REG(ch, 74), 394 (0x1 << 8) | (0x3 << 24), 395 (0x1 << 8) | (i << 24)); 396 while (1) { 397 /* PI_174 PI_INT_STATUS:RD:8:18 */ 398 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 399 400 /* 401 * make sure status obs not report error bit 402 * PHY_46/174/302/430 403 * phy_rdlvl_status_obs_X:16:8 404 */ 405 if ((((tmp >> 8) & 0x1) == 0x1) && 406 (((tmp >> 13) & 0x1) == 0x1) && 407 (((tmp >> 2) & 0x1) == 0x0)) 408 break; 409 else if (((tmp >> 2) & 0x1) == 0x1) 410 return -1; 411 } 412 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 413 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 414 } 415 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); 416 } 417 418 /* wdq leveling(LPDDR4 support) */ 419 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { 420 for (i = 0; i < 4; i++) { 421 if (!(rank_mask & (1 << i))) 422 continue; 423 424 select_per_cs_training_index(ch, i); 425 /* 426 * disable PI_WDQLVL_VREF_EN before wdq leveling? 427 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 428 */ 429 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); 430 /* PI_124 PI_WDQLVL_EN:RW:16:2 */ 431 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, 432 0x2 << 16); 433 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ 434 mmio_clrsetbits_32(PI_REG(ch, 121), 435 (0x1 << 8) | (0x3 << 16), 436 (0x1 << 8) | (i << 16)); 437 while (1) { 438 /* PI_174 PI_INT_STATUS:RD:8:18 */ 439 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 440 if ((((tmp >> 12) & 0x1) == 0x1) && 441 (((tmp >> 13) & 0x1) == 0x1) && 442 (((tmp >> 6) & 0x1) == 0x0)) 443 break; 444 else if (((tmp >> 6) & 0x1) == 0x1) 445 return -1; 446 } 447 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 448 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 449 } 450 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); 451 } 452 453 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 454 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); 455 456 return 0; 457 } 458 459 static __sramfunc void set_ddrconfig(struct rk3399_sdram_params *sdram_params, 460 unsigned char channel, uint32_t ddrconfig) 461 { 462 /* only need to set ddrconfig */ 463 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; 464 unsigned int cs0_cap = 0; 465 unsigned int cs1_cap = 0; 466 467 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20)); 468 if (ch->rank > 1) 469 cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row); 470 if (ch->row_3_4) { 471 cs0_cap = cs0_cap * 3 / 4; 472 cs1_cap = cs1_cap * 3 / 4; 473 } 474 475 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF, 476 ddrconfig | (ddrconfig << 6)); 477 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE, 478 ((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8)); 479 } 480 481 static __sramfunc void dram_all_config(struct rk3399_sdram_params *sdram_params) 482 { 483 unsigned int i; 484 485 for (i = 0; i < 2; i++) { 486 struct rk3399_sdram_channel *info = &sdram_params->ch[i]; 487 struct rk3399_msch_timings *noc = &info->noc_timings; 488 489 if (sdram_params->ch[i].col == 0) 490 continue; 491 492 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0, 493 noc->ddrtiminga0.d32); 494 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0, 495 noc->ddrtimingb0.d32); 496 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0, 497 noc->ddrtimingc0.d32); 498 mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0, 499 noc->devtodev0.d32); 500 mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32); 501 502 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ 503 if (sdram_params->ch[i].rank == 1) 504 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); 505 } 506 507 DDR_STRIDE(sdram_params->stride); 508 509 /* reboot hold register set */ 510 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 511 CRU_PMU_SGRF_RST_RLS | 512 PRESET_GPIO0_HOLD(1) | 513 PRESET_GPIO1_HOLD(1)); 514 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); 515 } 516 517 static __sramfunc void pctl_cfg(uint32_t ch, 518 struct rk3399_sdram_params *sdram_params) 519 { 520 const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl; 521 const uint32_t *params_phy = sdram_params->phy_regs.denali_phy; 522 const uint32_t *params_pi = sdram_params->pi_regs.denali_pi; 523 uint32_t tmp, tmp1, tmp2; 524 525 /* 526 * Workaround controller bug: 527 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed 528 */ 529 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1], 530 CTL_REG_NUM - 1); 531 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); 532 sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0], 533 PI_REG_NUM); 534 535 mmio_write_32(PHY_REG(ch, 910), params_phy[910]); 536 mmio_write_32(PHY_REG(ch, 911), params_phy[911]); 537 mmio_write_32(PHY_REG(ch, 912), params_phy[912]); 538 539 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, 540 PWRUP_SREFRESH_EXIT); 541 542 /* PHY_DLL_RST_EN */ 543 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24); 544 dmbst(); 545 546 mmio_setbits_32(PI_REG(ch, 0), START); 547 mmio_setbits_32(CTL_REG(ch, 0), START); 548 549 /* wait lock */ 550 while (1) { 551 tmp = mmio_read_32(PHY_REG(ch, 920)); 552 tmp1 = mmio_read_32(PHY_REG(ch, 921)); 553 tmp2 = mmio_read_32(PHY_REG(ch, 922)); 554 if ((((tmp >> 16) & 0x1) == 0x1) && 555 (((tmp1 >> 16) & 0x1) == 0x1) && 556 (((tmp1 >> 0) & 0x1) == 0x1) && 557 (((tmp2 >> 0) & 0x1) == 0x1)) 558 break; 559 /* if PLL bypass,don't need wait lock */ 560 if (mmio_read_32(PHY_REG(ch, 911)) & 0x1) 561 break; 562 } 563 564 sram_regcpy(PHY_REG(ch, 896), (uintptr_t)¶ms_phy[896], 63); 565 sram_regcpy(PHY_REG(ch, 0), (uintptr_t)¶ms_phy[0], 91); 566 sram_regcpy(PHY_REG(ch, 128), (uintptr_t)¶ms_phy[128], 91); 567 sram_regcpy(PHY_REG(ch, 256), (uintptr_t)¶ms_phy[256], 91); 568 sram_regcpy(PHY_REG(ch, 384), (uintptr_t)¶ms_phy[384], 91); 569 sram_regcpy(PHY_REG(ch, 512), (uintptr_t)¶ms_phy[512], 38); 570 sram_regcpy(PHY_REG(ch, 640), (uintptr_t)¶ms_phy[640], 38); 571 sram_regcpy(PHY_REG(ch, 768), (uintptr_t)¶ms_phy[768], 38); 572 } 573 574 static __sramfunc int dram_switch_to_phy_index1( 575 struct rk3399_sdram_params *sdram_params) 576 { 577 uint32_t ch, ch_count; 578 579 mmio_write_32(CIC_BASE + CIC_CTRL0, 580 (((0x3 << 4) | (1 << 2) | 1) << 16) | 581 (1 << 4) | (1 << 2) | 1); 582 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) 583 ; 584 585 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 586 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0))) 587 ; 588 589 ch_count = sdram_params->num_channels; 590 591 /* LPDDR4 f2 cann't do training, all training will fail */ 592 for (ch = 0; ch < ch_count; ch++) { 593 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, 594 1 << 8); 595 596 /* data_training failed */ 597 if (data_training(ch, sdram_params, PI_FULL_TRAINING)) 598 return -1; 599 } 600 601 return 0; 602 } 603 604 /* 605 * Needs to be done for both channels at once in case of a shared reset signal 606 * between channels. 607 */ 608 static __sramfunc int pctl_start(uint32_t channel_mask, 609 struct rk3399_sdram_params *sdram_params) 610 { 611 uint32_t count; 612 613 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 614 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 615 616 /* need de-access IO retention before controller START */ 617 if (channel_mask & (1 << 0)) 618 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); 619 if (channel_mask & (1 << 1)) 620 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); 621 622 /* PHY_DLL_RST_EN */ 623 if (channel_mask & (1 << 0)) 624 mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24, 625 0x2 << 24); 626 if (channel_mask & (1 << 1)) 627 mmio_clrsetbits_32(PHY_REG(1, 957), 0x3 << 24, 628 0x2 << 24); 629 630 /* check ERROR bit */ 631 if (channel_mask & (1 << 0)) { 632 count = 0; 633 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { 634 /* CKE is low, loop 10ms */ 635 if (count > 100) 636 return -1; 637 638 sram_udelay(100); 639 count++; 640 } 641 642 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 643 } 644 if (channel_mask & (1 << 1)) { 645 count = 0; 646 while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) { 647 /* CKE is low, loop 10ms */ 648 if (count > 100) 649 return -1; 650 651 sram_udelay(100); 652 count++; 653 } 654 655 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 656 } 657 658 return 0; 659 } 660 661 void dmc_save(void) 662 { 663 struct rk3399_sdram_params *sdram_params = &sdram_config; 664 uint32_t *params_ctl; 665 uint32_t *params_pi; 666 uint32_t *params_phy; 667 uint32_t refdiv, postdiv2, postdiv1, fbdiv; 668 uint32_t tmp; 669 670 params_ctl = sdram_params->pctl_regs.denali_ctl; 671 params_pi = sdram_params->pi_regs.denali_pi; 672 params_phy = sdram_params->phy_regs.denali_phy; 673 674 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 675 tmp = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)); 676 postdiv2 = POSTDIV2_DEC(tmp); 677 postdiv1 = POSTDIV1_DEC(tmp); 678 refdiv = REFDIV_DEC(tmp); 679 680 sdram_params->ddr_freq = ((fbdiv * 24) / 681 (refdiv * postdiv1 * postdiv2)) * MHz; 682 683 INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq); 684 sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) & 685 0x7) != 0) ? 1 : 0; 686 687 /* copy the registers CTL PI and PHY */ 688 sram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM); 689 690 /* mask DENALI_CTL_00_DATA.START, only copy here, will trigger later */ 691 params_ctl[0] &= ~(0x1 << 0); 692 693 sram_regcpy((uintptr_t)¶ms_pi[0], PI_REG(0, 0), 694 PI_REG_NUM); 695 696 /* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/ 697 params_pi[0] &= ~(0x1 << 0); 698 699 sram_regcpy((uintptr_t)¶ms_phy[0], PHY_REG(0, 0), 91); 700 sram_regcpy((uintptr_t)¶ms_phy[128], PHY_REG(0, 128), 91); 701 sram_regcpy((uintptr_t)¶ms_phy[256], PHY_REG(0, 256), 91); 702 sram_regcpy((uintptr_t)¶ms_phy[384], PHY_REG(0, 384), 91); 703 sram_regcpy((uintptr_t)¶ms_phy[512], PHY_REG(0, 512), 38); 704 sram_regcpy((uintptr_t)¶ms_phy[640], PHY_REG(0, 640), 38); 705 sram_regcpy((uintptr_t)¶ms_phy[768], PHY_REG(0, 768), 38); 706 sram_regcpy((uintptr_t)¶ms_phy[896], PHY_REG(0, 896), 63); 707 708 /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ 709 params_phy[957] &= ~(0x3 << 24); 710 params_phy[957] |= 1 << 24; 711 params_phy[896] |= 1; 712 params_phy[896] &= ~(0x3 << 8); 713 } 714 715 __sramfunc void dmc_restore(void) 716 { 717 struct rk3399_sdram_params *sdram_params = &sdram_config; 718 uint32_t channel_mask = 0; 719 uint32_t channel; 720 721 configure_sgrf(); 722 723 retry: 724 for (channel = 0; channel < sdram_params->num_channels; channel++) { 725 phy_pctrl_reset(channel); 726 phy_dll_bypass_set(channel, sdram_params->ddr_freq); 727 if (channel >= sdram_params->num_channels) 728 continue; 729 730 pctl_cfg(channel, sdram_params); 731 } 732 733 for (channel = 0; channel < 2; channel++) { 734 if (sdram_params->ch[channel].col) 735 channel_mask |= 1 << channel; 736 } 737 738 if (pctl_start(channel_mask, sdram_params) < 0) 739 goto retry; 740 741 for (channel = 0; channel < sdram_params->num_channels; channel++) { 742 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 743 if (sdram_params->dramtype == LPDDR3) 744 sram_udelay(10); 745 746 /* If traning fail, retry to do it again. */ 747 if (data_training(channel, sdram_params, PI_FULL_TRAINING)) 748 goto retry; 749 750 set_ddrconfig(sdram_params, channel, 751 sdram_params->ch[channel].ddrconfig); 752 } 753 754 dram_all_config(sdram_params); 755 756 /* Switch to index 1 and prepare for DDR frequency switch. */ 757 dram_switch_to_phy_index1(sdram_params); 758 } 759