1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <dram.h> 10 #include <plat_private.h> 11 #include <platform_def.h> 12 #include <pmu_regs.h> 13 #include <rk3399_def.h> 14 #include <secure.h> 15 #include <soc.h> 16 #include <suspend.h> 17 18 #define PMUGRF_OS_REG0 0x300 19 #define PMUGRF_OS_REG1 0x304 20 #define PMUGRF_OS_REG2 0x308 21 #define PMUGRF_OS_REG3 0x30c 22 23 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ 24 ((n) << (8 + (ch) * 4))) 25 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ 26 ((n) << (9 + (ch) * 4))) 27 28 #define FBDIV_ENC(n) ((n) << 16) 29 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) 30 #define POSTDIV2_ENC(n) ((n) << 12) 31 #define POSTDIV2_DEC(n) (((n) >> 12) & 0x7) 32 #define POSTDIV1_ENC(n) ((n) << 8) 33 #define POSTDIV1_DEC(n) (((n) >> 8) & 0x7) 34 #define REFDIV_ENC(n) (n) 35 #define REFDIV_DEC(n) ((n) & 0x3f) 36 37 /* PMU CRU */ 38 #define PMUCRU_RSTNHOLD_CON0 0x120 39 #define PMUCRU_RSTNHOLD_CON1 0x124 40 41 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7)) 42 #define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8)) 43 44 #define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000) 45 46 /* 47 * Copy @num registers from @src to @dst 48 */ 49 static __pmusramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, 50 uint32_t num) 51 { 52 while (num--) { 53 mmio_write_32(dst, mmio_read_32(src)); 54 dst += sizeof(uint32_t); 55 src += sizeof(uint32_t); 56 } 57 } 58 59 /* 60 * Copy @num registers from @src to @dst 61 * This is intentionally a copy of the sram_regcpy function. PMUSRAM functions 62 * cannot be called from code running in DRAM. 63 */ 64 static void dram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num) 65 { 66 while (num--) { 67 mmio_write_32(dst, mmio_read_32(src)); 68 dst += sizeof(uint32_t); 69 src += sizeof(uint32_t); 70 } 71 } 72 73 static __pmusramfunc uint32_t sram_get_timer_value(void) 74 { 75 /* 76 * Generic delay timer implementation expects the timer to be a down 77 * counter. We apply bitwise NOT operator to the tick values returned 78 * by read_cntpct_el0() to simulate the down counter. 79 */ 80 return (uint32_t)(~read_cntpct_el0()); 81 } 82 83 static __pmusramfunc void sram_udelay(uint32_t usec) 84 { 85 uint32_t start, cnt, delta, delta_us; 86 87 /* counter is decreasing */ 88 start = sram_get_timer_value(); 89 do { 90 cnt = sram_get_timer_value(); 91 if (cnt > start) { 92 delta = UINT32_MAX - cnt; 93 delta += start; 94 } else 95 delta = start - cnt; 96 delta_us = (delta * SYS_COUNTER_FREQ_IN_MHZ); 97 } while (delta_us < usec); 98 } 99 100 static __pmusramfunc void configure_sgrf(void) 101 { 102 /* 103 * SGRF_DDR_RGN_DPLL_CLK and SGRF_DDR_RGN_RTC_CLK: 104 * IC ECO bug, need to set this register. 105 * 106 * SGRF_DDR_RGN_BYPS: 107 * After the PD_CENTER suspend/resume, the DDR region 108 * related registers in the SGRF will be reset, we 109 * need to re-initialize them. 110 */ 111 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 112 SGRF_DDR_RGN_DPLL_CLK | 113 SGRF_DDR_RGN_RTC_CLK | 114 SGRF_DDR_RGN_BYPS); 115 } 116 117 static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, 118 uint32_t phy) 119 { 120 channel &= 0x1; 121 ctl &= 0x1; 122 phy &= 0x1; 123 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), 124 CRU_SFTRST_DDR_CTRL(channel, ctl) | 125 CRU_SFTRST_DDR_PHY(channel, phy)); 126 } 127 128 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) 129 { 130 rkclk_ddr_reset(ch, 1, 1); 131 sram_udelay(10); 132 rkclk_ddr_reset(ch, 1, 0); 133 sram_udelay(10); 134 rkclk_ddr_reset(ch, 0, 0); 135 sram_udelay(10); 136 } 137 138 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) 139 { 140 uint32_t byte; 141 142 /* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */ 143 for (byte = 0; byte < 4; byte++) 144 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, 145 rank << 24); 146 } 147 148 static __pmusramfunc void select_per_cs_training_index(uint32_t ch, 149 uint32_t rank) 150 { 151 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ 152 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) 153 set_cs_training_index(ch, rank); 154 } 155 156 static __pmusramfunc void override_write_leveling_value(uint32_t ch) 157 { 158 uint32_t byte; 159 160 for (byte = 0; byte < 4; byte++) { 161 /* 162 * PHY_8/136/264/392 163 * phy_per_cs_training_multicast_en_X 1bit offset_16 164 */ 165 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, 166 1 << 16); 167 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), 168 0xffff << 16, 169 0x200 << 16); 170 } 171 172 /* CTL_200 ctrlupd_req 1bit offset_8 */ 173 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); 174 } 175 176 static __pmusramfunc int data_training(uint32_t ch, 177 struct rk3399_sdram_params *sdram_params, 178 uint32_t training_flag) 179 { 180 uint32_t obs_0, obs_1, obs_2, obs_3, obs_err = 0; 181 uint32_t rank = sdram_params->ch[ch].rank; 182 uint32_t rank_mask; 183 uint32_t i, tmp; 184 185 if (sdram_params->dramtype == LPDDR4) 186 rank_mask = (rank == 1) ? 0x5 : 0xf; 187 else 188 rank_mask = (rank == 1) ? 0x1 : 0x3; 189 190 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 191 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); 192 193 if (training_flag == PI_FULL_TRAINING) { 194 if (sdram_params->dramtype == LPDDR4) { 195 training_flag = PI_WRITE_LEVELING | 196 PI_READ_GATE_TRAINING | 197 PI_READ_LEVELING | 198 PI_WDQ_LEVELING; 199 } else if (sdram_params->dramtype == LPDDR3) { 200 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 201 PI_READ_GATE_TRAINING; 202 } else if (sdram_params->dramtype == DDR3) { 203 training_flag = PI_WRITE_LEVELING | 204 PI_READ_GATE_TRAINING | 205 PI_READ_LEVELING; 206 } 207 } 208 209 /* ca training(LPDDR4,LPDDR3 support) */ 210 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { 211 for (i = 0; i < 4; i++) { 212 if (!(rank_mask & (1 << i))) 213 continue; 214 215 select_per_cs_training_index(ch, i); 216 /* PI_100 PI_CALVL_EN:RW:8:2 */ 217 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); 218 219 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ 220 mmio_clrsetbits_32(PI_REG(ch, 92), 221 (0x1 << 16) | (0x3 << 24), 222 (0x1 << 16) | (i << 24)); 223 while (1) { 224 /* PI_174 PI_INT_STATUS:RD:8:18 */ 225 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 226 227 /* 228 * check status obs 229 * PHY_532/660/788 phy_adr_calvl_obs1_:0:32 230 */ 231 obs_0 = mmio_read_32(PHY_REG(ch, 532)); 232 obs_1 = mmio_read_32(PHY_REG(ch, 660)); 233 obs_2 = mmio_read_32(PHY_REG(ch, 788)); 234 if (((obs_0 >> 30) & 0x3) || 235 ((obs_1 >> 30) & 0x3) || 236 ((obs_2 >> 30) & 0x3)) 237 obs_err = 1; 238 if ((((tmp >> 11) & 0x1) == 0x1) && 239 (((tmp >> 13) & 0x1) == 0x1) && 240 (((tmp >> 5) & 0x1) == 0x0) && 241 (obs_err == 0)) 242 break; 243 else if ((((tmp >> 5) & 0x1) == 0x1) || 244 (obs_err == 1)) 245 return -1; 246 } 247 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 248 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 249 } 250 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); 251 } 252 253 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ 254 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { 255 for (i = 0; i < rank; i++) { 256 select_per_cs_training_index(ch, i); 257 /* PI_60 PI_WRLVL_EN:RW:8:2 */ 258 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); 259 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ 260 mmio_clrsetbits_32(PI_REG(ch, 59), 261 (0x1 << 8) | (0x3 << 16), 262 (0x1 << 8) | (i << 16)); 263 264 while (1) { 265 /* PI_174 PI_INT_STATUS:RD:8:18 */ 266 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 267 268 /* 269 * check status obs, if error maybe can not 270 * get leveling done PHY_40/168/296/424 271 * phy_wrlvl_status_obs_X:0:13 272 */ 273 obs_0 = mmio_read_32(PHY_REG(ch, 40)); 274 obs_1 = mmio_read_32(PHY_REG(ch, 168)); 275 obs_2 = mmio_read_32(PHY_REG(ch, 296)); 276 obs_3 = mmio_read_32(PHY_REG(ch, 424)); 277 if (((obs_0 >> 12) & 0x1) || 278 ((obs_1 >> 12) & 0x1) || 279 ((obs_2 >> 12) & 0x1) || 280 ((obs_3 >> 12) & 0x1)) 281 obs_err = 1; 282 if ((((tmp >> 10) & 0x1) == 0x1) && 283 (((tmp >> 13) & 0x1) == 0x1) && 284 (((tmp >> 4) & 0x1) == 0x0) && 285 (obs_err == 0)) 286 break; 287 else if ((((tmp >> 4) & 0x1) == 0x1) || 288 (obs_err == 1)) 289 return -1; 290 } 291 292 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 293 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 294 } 295 override_write_leveling_value(ch); 296 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); 297 } 298 299 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ 300 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { 301 for (i = 0; i < rank; i++) { 302 select_per_cs_training_index(ch, i); 303 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ 304 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, 305 0x2 << 24); 306 /* 307 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 308 * PI_RDLVL_CS:RW:24:2 309 */ 310 mmio_clrsetbits_32(PI_REG(ch, 74), 311 (0x1 << 16) | (0x3 << 24), 312 (0x1 << 16) | (i << 24)); 313 314 while (1) { 315 /* PI_174 PI_INT_STATUS:RD:8:18 */ 316 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 317 318 /* 319 * check status obs 320 * PHY_43/171/299/427 321 * PHY_GTLVL_STATUS_OBS_x:16:8 322 */ 323 obs_0 = mmio_read_32(PHY_REG(ch, 43)); 324 obs_1 = mmio_read_32(PHY_REG(ch, 171)); 325 obs_2 = mmio_read_32(PHY_REG(ch, 299)); 326 obs_3 = mmio_read_32(PHY_REG(ch, 427)); 327 if (((obs_0 >> (16 + 6)) & 0x3) || 328 ((obs_1 >> (16 + 6)) & 0x3) || 329 ((obs_2 >> (16 + 6)) & 0x3) || 330 ((obs_3 >> (16 + 6)) & 0x3)) 331 obs_err = 1; 332 if ((((tmp >> 9) & 0x1) == 0x1) && 333 (((tmp >> 13) & 0x1) == 0x1) && 334 (((tmp >> 3) & 0x1) == 0x0) && 335 (obs_err == 0)) 336 break; 337 else if ((((tmp >> 3) & 0x1) == 0x1) || 338 (obs_err == 1)) 339 return -1; 340 } 341 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 342 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 343 } 344 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); 345 } 346 347 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ 348 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { 349 for (i = 0; i < rank; i++) { 350 select_per_cs_training_index(ch, i); 351 /* PI_80 PI_RDLVL_EN:RW:16:2 */ 352 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, 353 0x2 << 16); 354 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ 355 mmio_clrsetbits_32(PI_REG(ch, 74), 356 (0x1 << 8) | (0x3 << 24), 357 (0x1 << 8) | (i << 24)); 358 while (1) { 359 /* PI_174 PI_INT_STATUS:RD:8:18 */ 360 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 361 362 /* 363 * make sure status obs not report error bit 364 * PHY_46/174/302/430 365 * phy_rdlvl_status_obs_X:16:8 366 */ 367 if ((((tmp >> 8) & 0x1) == 0x1) && 368 (((tmp >> 13) & 0x1) == 0x1) && 369 (((tmp >> 2) & 0x1) == 0x0)) 370 break; 371 else if (((tmp >> 2) & 0x1) == 0x1) 372 return -1; 373 } 374 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 375 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 376 } 377 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); 378 } 379 380 /* wdq leveling(LPDDR4 support) */ 381 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { 382 for (i = 0; i < 4; i++) { 383 if (!(rank_mask & (1 << i))) 384 continue; 385 386 select_per_cs_training_index(ch, i); 387 /* 388 * disable PI_WDQLVL_VREF_EN before wdq leveling? 389 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 390 */ 391 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); 392 /* PI_124 PI_WDQLVL_EN:RW:16:2 */ 393 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, 394 0x2 << 16); 395 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ 396 mmio_clrsetbits_32(PI_REG(ch, 121), 397 (0x1 << 8) | (0x3 << 16), 398 (0x1 << 8) | (i << 16)); 399 while (1) { 400 /* PI_174 PI_INT_STATUS:RD:8:18 */ 401 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; 402 if ((((tmp >> 12) & 0x1) == 0x1) && 403 (((tmp >> 13) & 0x1) == 0x1) && 404 (((tmp >> 6) & 0x1) == 0x0)) 405 break; 406 else if (((tmp >> 6) & 0x1) == 0x1) 407 return -1; 408 } 409 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 410 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); 411 } 412 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); 413 } 414 415 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 416 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); 417 418 return 0; 419 } 420 421 static __pmusramfunc void set_ddrconfig( 422 struct rk3399_sdram_params *sdram_params, 423 unsigned char channel, uint32_t ddrconfig) 424 { 425 /* only need to set ddrconfig */ 426 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; 427 unsigned int cs0_cap = 0; 428 unsigned int cs1_cap = 0; 429 430 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20)); 431 if (ch->rank > 1) 432 cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row); 433 if (ch->row_3_4) { 434 cs0_cap = cs0_cap * 3 / 4; 435 cs1_cap = cs1_cap * 3 / 4; 436 } 437 438 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF, 439 ddrconfig | (ddrconfig << 6)); 440 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE, 441 ((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8)); 442 } 443 444 static __pmusramfunc void dram_all_config( 445 struct rk3399_sdram_params *sdram_params) 446 { 447 unsigned int i; 448 449 for (i = 0; i < 2; i++) { 450 struct rk3399_sdram_channel *info = &sdram_params->ch[i]; 451 struct rk3399_msch_timings *noc = &info->noc_timings; 452 453 if (sdram_params->ch[i].col == 0) 454 continue; 455 456 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0, 457 noc->ddrtiminga0.d32); 458 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0, 459 noc->ddrtimingb0.d32); 460 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0, 461 noc->ddrtimingc0.d32); 462 mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0, 463 noc->devtodev0.d32); 464 mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32); 465 466 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ 467 if (sdram_params->ch[i].rank == 1) 468 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); 469 } 470 471 DDR_STRIDE(sdram_params->stride); 472 473 /* reboot hold register set */ 474 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 475 CRU_PMU_SGRF_RST_RLS | 476 PRESET_GPIO0_HOLD(1) | 477 PRESET_GPIO1_HOLD(1)); 478 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); 479 } 480 481 static __pmusramfunc void pctl_cfg(uint32_t ch, 482 struct rk3399_sdram_params *sdram_params) 483 { 484 const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl; 485 const uint32_t *params_pi = sdram_params->pi_regs.denali_pi; 486 const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs; 487 uint32_t tmp, tmp1, tmp2, i; 488 489 /* 490 * Workaround controller bug: 491 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed 492 */ 493 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1], 494 CTL_REG_NUM - 1); 495 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); 496 sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0], 497 PI_REG_NUM); 498 499 sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896], 500 3); 501 502 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, 503 PWRUP_SREFRESH_EXIT); 504 505 /* PHY_DLL_RST_EN */ 506 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24); 507 dmbst(); 508 509 mmio_setbits_32(PI_REG(ch, 0), START); 510 mmio_setbits_32(CTL_REG(ch, 0), START); 511 512 /* wait lock */ 513 while (1) { 514 tmp = mmio_read_32(PHY_REG(ch, 920)); 515 tmp1 = mmio_read_32(PHY_REG(ch, 921)); 516 tmp2 = mmio_read_32(PHY_REG(ch, 922)); 517 if ((((tmp >> 16) & 0x1) == 0x1) && 518 (((tmp1 >> 16) & 0x1) == 0x1) && 519 (((tmp1 >> 0) & 0x1) == 0x1) && 520 (((tmp2 >> 0) & 0x1) == 0x1)) 521 break; 522 /* if PLL bypass,don't need wait lock */ 523 if (mmio_read_32(PHY_REG(ch, 911)) & 0x1) 524 break; 525 } 526 527 sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63); 528 529 for (i = 0; i < 4; i++) 530 sram_regcpy(PHY_REG(ch, 128 * i), 531 (uintptr_t)&phy_regs->phy0[i][0], 91); 532 533 for (i = 0; i < 3; i++) 534 sram_regcpy(PHY_REG(ch, 512 + 128 * i), 535 (uintptr_t)&phy_regs->phy512[i][0], 38); 536 } 537 538 static __pmusramfunc int dram_switch_to_next_index( 539 struct rk3399_sdram_params *sdram_params) 540 { 541 uint32_t ch, ch_count; 542 uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; 543 544 mmio_write_32(CIC_BASE + CIC_CTRL0, 545 (((0x3 << 4) | (1 << 2) | 1) << 16) | 546 (fn << 4) | (1 << 2) | 1); 547 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) 548 ; 549 550 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 551 while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0))) 552 ; 553 554 ch_count = sdram_params->num_channels; 555 556 /* LPDDR4 f2 cann't do training, all training will fail */ 557 for (ch = 0; ch < ch_count; ch++) { 558 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, 559 fn << 8); 560 561 /* data_training failed */ 562 if (data_training(ch, sdram_params, PI_FULL_TRAINING)) 563 return -1; 564 } 565 566 return 0; 567 } 568 569 /* 570 * Needs to be done for both channels at once in case of a shared reset signal 571 * between channels. 572 */ 573 static __pmusramfunc int pctl_start(uint32_t channel_mask, 574 struct rk3399_sdram_params *sdram_params) 575 { 576 uint32_t count; 577 uint32_t byte; 578 579 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 580 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 581 582 /* need de-access IO retention before controller START */ 583 if (channel_mask & (1 << 0)) 584 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); 585 if (channel_mask & (1 << 1)) 586 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); 587 588 /* PHY_DLL_RST_EN */ 589 if (channel_mask & (1 << 0)) 590 mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24, 591 0x2 << 24); 592 if (channel_mask & (1 << 1)) 593 mmio_clrsetbits_32(PHY_REG(1, 957), 0x3 << 24, 594 0x2 << 24); 595 596 /* check ERROR bit */ 597 if (channel_mask & (1 << 0)) { 598 count = 0; 599 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { 600 /* CKE is low, loop 10ms */ 601 if (count > 100) 602 return -1; 603 604 sram_udelay(100); 605 count++; 606 } 607 608 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); 609 610 /* Restore the PHY_RX_CAL_DQS value */ 611 for (byte = 0; byte < 4; byte++) 612 mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte), 613 0xfff << 16, 614 sdram_params->rx_cal_dqs[0][byte]); 615 } 616 if (channel_mask & (1 << 1)) { 617 count = 0; 618 while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) { 619 /* CKE is low, loop 10ms */ 620 if (count > 100) 621 return -1; 622 623 sram_udelay(100); 624 count++; 625 } 626 627 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); 628 629 /* Restore the PHY_RX_CAL_DQS value */ 630 for (byte = 0; byte < 4; byte++) 631 mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte), 632 0xfff << 16, 633 sdram_params->rx_cal_dqs[1][byte]); 634 } 635 636 return 0; 637 } 638 639 void dmc_save(void) 640 { 641 struct rk3399_sdram_params *sdram_params = &sdram_config; 642 struct rk3399_ddr_publ_regs *phy_regs; 643 uint32_t *params_ctl; 644 uint32_t *params_pi; 645 uint32_t refdiv, postdiv2, postdiv1, fbdiv; 646 uint32_t tmp, ch, byte, i; 647 648 phy_regs = &sdram_params->phy_regs; 649 params_ctl = sdram_params->pctl_regs.denali_ctl; 650 params_pi = sdram_params->pi_regs.denali_pi; 651 652 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 653 tmp = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)); 654 postdiv2 = POSTDIV2_DEC(tmp); 655 postdiv1 = POSTDIV1_DEC(tmp); 656 refdiv = REFDIV_DEC(tmp); 657 658 sdram_params->ddr_freq = ((fbdiv * 24) / 659 (refdiv * postdiv1 * postdiv2)) * MHz; 660 661 INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq); 662 sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) & 663 0x7) != 0) ? 1 : 0; 664 665 /* copy the registers CTL PI and PHY */ 666 dram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM); 667 668 /* mask DENALI_CTL_00_DATA.START, only copy here, will trigger later */ 669 params_ctl[0] &= ~(0x1 << 0); 670 671 dram_regcpy((uintptr_t)¶ms_pi[0], PI_REG(0, 0), 672 PI_REG_NUM); 673 674 /* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/ 675 params_pi[0] &= ~(0x1 << 0); 676 677 for (i = 0; i < 4; i++) 678 dram_regcpy((uintptr_t)&phy_regs->phy0[i][0], 679 PHY_REG(0, 128 * i), 91); 680 681 for (i = 0; i < 3; i++) 682 dram_regcpy((uintptr_t)&phy_regs->phy512[i][0], 683 PHY_REG(0, 512 + 128 * i), 38); 684 685 dram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63); 686 687 for (ch = 0; ch < sdram_params->num_channels; ch++) { 688 for (byte = 0; byte < 4; byte++) 689 sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) & 690 mmio_read_32(PHY_REG(ch, 57 + byte * 128)); 691 } 692 693 /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ 694 phy_regs->phy896[957 - 896] &= ~(0x3 << 24); 695 phy_regs->phy896[957 - 896] |= 1 << 24; 696 phy_regs->phy896[0] |= 1; 697 phy_regs->phy896[0] &= ~(0x3 << 8); 698 } 699 700 __pmusramfunc void dmc_restore(void) 701 { 702 struct rk3399_sdram_params *sdram_params = &sdram_config; 703 uint32_t channel_mask = 0; 704 uint32_t channel; 705 706 configure_sgrf(); 707 708 retry: 709 for (channel = 0; channel < sdram_params->num_channels; channel++) { 710 phy_pctrl_reset(channel); 711 pctl_cfg(channel, sdram_params); 712 } 713 714 for (channel = 0; channel < 2; channel++) { 715 if (sdram_params->ch[channel].col) 716 channel_mask |= 1 << channel; 717 } 718 719 if (pctl_start(channel_mask, sdram_params) < 0) 720 goto retry; 721 722 for (channel = 0; channel < sdram_params->num_channels; channel++) { 723 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 724 if (sdram_params->dramtype == LPDDR3) 725 sram_udelay(10); 726 727 /* If traning fail, retry to do it again. */ 728 if (data_training(channel, sdram_params, PI_FULL_TRAINING)) 729 goto retry; 730 731 set_ddrconfig(sdram_params, channel, 732 sdram_params->ch[channel].ddrconfig); 733 } 734 735 dram_all_config(sdram_params); 736 737 /* Switch to index 1 and prepare for DDR frequency switch. */ 738 dram_switch_to_next_index(sdram_params); 739 } 740