1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_PRIVATE_H__ 32 #define __PLAT_PRIVATE_H__ 33 34 #ifndef __ASSEMBLY__ 35 #include <mmio.h> 36 #include <stdint.h> 37 #include <xlat_tables.h> 38 39 /****************************************************************************** 40 * For rockchip socs pm ops 41 ******************************************************************************/ 42 struct rockchip_pm_ops_cb { 43 int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint); 44 int (*cores_pwr_dm_off)(void); 45 int (*cores_pwr_dm_on_finish)(void); 46 int (*cores_pwr_dm_suspend)(void); 47 int (*cores_pwr_dm_resume)(void); 48 int (*sys_pwr_dm_suspend)(void); 49 int (*sys_pwr_dm_resume)(void); 50 void (*sys_gbl_soft_reset)(void) __dead2; 51 void (*system_off)(void) __dead2; 52 }; 53 54 /****************************************************************************** 55 * The register have write-mask bits, it is mean, if you want to set the bits, 56 * you needs set the write-mask bits at the same time, 57 * The write-mask bits is in high 16-bits. 58 * The fllowing macro definition helps access write-mask bits reg efficient! 59 ******************************************************************************/ 60 #define REG_MSK_SHIFT 16 61 62 #ifndef BIT 63 #define BIT(nr) (1 << (nr)) 64 #endif 65 66 #ifndef WMSK_BIT 67 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 68 #endif 69 70 /* set one bit with write mask */ 71 #ifndef BIT_WITH_WMSK 72 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 73 #endif 74 75 #ifndef BITS_SHIFT 76 #define BITS_SHIFT(bits, shift) (bits << (shift)) 77 #endif 78 79 #ifndef BITS_WITH_WMASK 80 #define BITS_WITH_WMASK(bits, msk, shift)\ 81 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 82 #endif 83 84 /****************************************************************************** 85 * Function and variable prototypes 86 *****************************************************************************/ 87 void plat_configure_mmu_el3(unsigned long total_base, 88 unsigned long total_size, 89 unsigned long, 90 unsigned long, 91 unsigned long, 92 unsigned long); 93 94 void plat_cci_init(void); 95 void plat_cci_enable(void); 96 void plat_cci_disable(void); 97 98 void plat_delay_timer_init(void); 99 100 void params_early_setup(void *plat_params_from_bl2); 101 102 void plat_rockchip_gic_driver_init(void); 103 void plat_rockchip_gic_init(void); 104 void plat_rockchip_gic_cpuif_enable(void); 105 void plat_rockchip_gic_cpuif_disable(void); 106 void plat_rockchip_gic_pcpu_init(void); 107 108 void plat_rockchip_pmusram_prepare(void); 109 void plat_rockchip_pmu_init(void); 110 void plat_rockchip_soc_init(void); 111 void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops); 112 113 void platform_cpu_warmboot(void); 114 115 void *plat_get_rockchip_gpio_reset(void); 116 void *plat_get_rockchip_gpio_poweroff(void); 117 void plat_rockchip_gpio_init(void); 118 119 extern const unsigned char rockchip_power_domain_tree_desc[]; 120 121 extern void *pmu_cpuson_entrypoint_start; 122 extern void *pmu_cpuson_entrypoint_end; 123 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 124 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 125 126 extern const mmap_region_t plat_rk_mmap[]; 127 #endif /* __ASSEMBLY__ */ 128 129 /* only Cortex-A53 */ 130 #define RK_PLAT_CFG0 0 131 132 /* include Cortex-A72 */ 133 #define RK_PLAT_CFG1 1 134 135 #endif /* __PLAT_PRIVATE_H__ */ 136