1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_PRIVATE_H 8 #define PLAT_PRIVATE_H 9 10 #ifndef __ASSEMBLY__ 11 12 #include <stdint.h> 13 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 #include <lib/mmio.h> 17 18 #define __sramdata __attribute__((section(".sram.data"))) 19 #define __sramconst __attribute__((section(".sram.rodata"))) 20 #define __sramfunc __attribute__((section(".sram.text"))) 21 22 #define __pmusramdata __attribute__((section(".pmusram.data"))) 23 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 24 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 25 26 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 27 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 28 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 29 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; 30 extern uint32_t __sram_incbin_start, __sram_incbin_end; 31 extern uint32_t __sram_incbin_real_end; 32 33 struct rockchip_bl31_params { 34 param_header_t h; 35 image_info_t *bl31_image_info; 36 entry_point_info_t *bl32_ep_info; 37 image_info_t *bl32_image_info; 38 entry_point_info_t *bl33_ep_info; 39 image_info_t *bl33_image_info; 40 }; 41 42 /****************************************************************************** 43 * The register have write-mask bits, it is mean, if you want to set the bits, 44 * you needs set the write-mask bits at the same time, 45 * The write-mask bits is in high 16-bits. 46 * The fllowing macro definition helps access write-mask bits reg efficient! 47 ******************************************************************************/ 48 #define REG_MSK_SHIFT 16 49 50 #ifndef WMSK_BIT 51 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 52 #endif 53 54 /* set one bit with write mask */ 55 #ifndef BIT_WITH_WMSK 56 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 57 #endif 58 59 #ifndef BITS_SHIFT 60 #define BITS_SHIFT(bits, shift) (bits << (shift)) 61 #endif 62 63 #ifndef BITS_WITH_WMASK 64 #define BITS_WITH_WMASK(bits, msk, shift)\ 65 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 66 #endif 67 68 /****************************************************************************** 69 * Function and variable prototypes 70 *****************************************************************************/ 71 #ifdef AARCH32 72 void plat_configure_mmu_svc_mon(unsigned long total_base, 73 unsigned long total_size, 74 unsigned long, 75 unsigned long, 76 unsigned long, 77 unsigned long); 78 79 void rockchip_plat_mmu_svc_mon(void); 80 #else 81 void plat_configure_mmu_el3(unsigned long total_base, 82 unsigned long total_size, 83 unsigned long, 84 unsigned long, 85 unsigned long, 86 unsigned long); 87 88 void rockchip_plat_mmu_el3(void); 89 #endif 90 91 void plat_cci_init(void); 92 void plat_cci_enable(void); 93 void plat_cci_disable(void); 94 95 void plat_delay_timer_init(void); 96 97 void params_early_setup(void *plat_params_from_bl2); 98 99 void plat_rockchip_gic_driver_init(void); 100 void plat_rockchip_gic_init(void); 101 void plat_rockchip_gic_cpuif_enable(void); 102 void plat_rockchip_gic_cpuif_disable(void); 103 void plat_rockchip_gic_pcpu_init(void); 104 105 void plat_rockchip_pmu_init(void); 106 void plat_rockchip_soc_init(void); 107 uintptr_t plat_get_sec_entrypoint(void); 108 109 void platform_cpu_warmboot(void); 110 111 struct gpio_info *plat_get_rockchip_gpio_reset(void); 112 struct gpio_info *plat_get_rockchip_gpio_poweroff(void); 113 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 114 struct apio_info *plat_get_rockchip_suspend_apio(void); 115 void plat_rockchip_gpio_init(void); 116 void plat_rockchip_save_gpio(void); 117 void plat_rockchip_restore_gpio(void); 118 119 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 120 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 121 plat_local_state_t lvl_state); 122 int rockchip_soc_cores_pwr_dm_off(void); 123 int rockchip_soc_sys_pwr_dm_suspend(void); 124 int rockchip_soc_cores_pwr_dm_suspend(void); 125 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 126 plat_local_state_t lvl_state); 127 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 128 plat_local_state_t lvl_state); 129 int rockchip_soc_cores_pwr_dm_on_finish(void); 130 int rockchip_soc_sys_pwr_dm_resume(void); 131 132 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 133 plat_local_state_t lvl_state); 134 int rockchip_soc_cores_pwr_dm_resume(void); 135 void __dead2 rockchip_soc_soft_reset(void); 136 void __dead2 rockchip_soc_system_off(void); 137 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 138 const psci_power_state_t *target_state); 139 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 140 141 extern const unsigned char rockchip_power_domain_tree_desc[]; 142 143 extern void *pmu_cpuson_entrypoint; 144 extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 145 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 146 147 extern const mmap_region_t plat_rk_mmap[]; 148 149 uint32_t rockchip_get_uart_base(void); 150 151 #endif /* __ASSEMBLY__ */ 152 153 /****************************************************************************** 154 * cpu up status 155 * The bits of macro value is not more than 12 bits for cmp instruction! 156 ******************************************************************************/ 157 #define PMU_CPU_HOTPLUG 0xf00 158 #define PMU_CPU_AUTO_PWRDN 0xf0 159 #define PMU_CLST_RET 0xa5 160 161 #endif /* PLAT_PRIVATE_H */ 162