1 /* 2 * Copyright (c) 2014-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_PRIVATE_H 8 #define PLAT_PRIVATE_H 9 10 #ifndef __ASSEMBLER__ 11 12 #include <stdint.h> 13 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat_params.h> 18 19 #define __sramdata __attribute__((section(".sram.data"))) 20 #define __sramconst __attribute__((section(".sram.rodata"))) 21 #define __sramfunc __attribute__((section(".sram.text"))) 22 23 #define __pmusramdata __attribute__((section(".pmusram.data"))) 24 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 25 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 26 27 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 28 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 29 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 30 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; 31 extern uint32_t __bl31_pmusram_text_start, __bl31_pmusram_text_end; 32 extern uint32_t __bl31_pmusram_data_start, __bl31_pmusram_data_end; 33 extern uint32_t __bl31_pmusram_text_real_end, __bl31_pmusram_data_real_end; 34 extern uint32_t __sram_incbin_start, __sram_incbin_end; 35 extern uint32_t __sram_incbin_real_end; 36 37 /****************************************************************************** 38 * The register have write-mask bits, it is mean, if you want to set the bits, 39 * you needs set the write-mask bits at the same time, 40 * The write-mask bits is in high 16-bits. 41 * The fllowing macro definition helps access write-mask bits reg efficient! 42 ******************************************************************************/ 43 #define REG_MSK_SHIFT 16 44 45 #ifndef WMSK_BIT 46 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 47 #endif 48 49 /* set one bit with write mask */ 50 #ifndef BIT_WITH_WMSK 51 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 52 #endif 53 54 #ifndef BITS_SHIFT 55 #define BITS_SHIFT(bits, shift) ((bits) << (shift)) 56 #endif 57 58 #ifndef BITS_WITH_WMASK 59 #define BITS_WITH_WMASK(bits, msk, shift)\ 60 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 61 #endif 62 63 /****************************************************************************** 64 * Function and variable prototypes 65 *****************************************************************************/ 66 #ifdef __aarch64__ 67 void plat_configure_mmu_el3(unsigned long total_base, 68 unsigned long total_size, 69 unsigned long, 70 unsigned long, 71 unsigned long, 72 unsigned long); 73 74 void rockchip_plat_mmu_el3(void); 75 #else 76 void plat_configure_mmu_svc_mon(unsigned long total_base, 77 unsigned long total_size, 78 unsigned long, 79 unsigned long, 80 unsigned long, 81 unsigned long); 82 83 void rockchip_plat_mmu_svc_mon(void); 84 #endif 85 86 void plat_cci_init(void); 87 void plat_cci_enable(void); 88 void plat_cci_disable(void); 89 90 void plat_delay_timer_init(void); 91 92 void params_early_setup(u_register_t plat_params_from_bl2); 93 94 void plat_rockchip_gic_driver_init(void); 95 void plat_rockchip_gic_init(void); 96 void plat_rockchip_gic_cpuif_enable(void); 97 void plat_rockchip_gic_cpuif_disable(void); 98 void plat_rockchip_gic_pcpu_init(void); 99 100 void plat_rockchip_pmu_init(void); 101 void plat_rockchip_soc_init(void); 102 uintptr_t plat_get_sec_entrypoint(void); 103 104 void platform_cpu_warmboot(void); 105 106 struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void); 107 struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void); 108 struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 109 struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void); 110 void plat_rockchip_gpio_init(void); 111 void plat_rockchip_save_gpio(void); 112 void plat_rockchip_restore_gpio(void); 113 114 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 115 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 116 plat_local_state_t lvl_state); 117 int rockchip_soc_cores_pwr_dm_off(void); 118 int rockchip_soc_sys_pwr_dm_suspend(void); 119 int rockchip_soc_cores_pwr_dm_suspend(void); 120 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 121 plat_local_state_t lvl_state); 122 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 123 plat_local_state_t lvl_state); 124 int rockchip_soc_cores_pwr_dm_on_finish(void); 125 int rockchip_soc_sys_pwr_dm_resume(void); 126 127 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 128 plat_local_state_t lvl_state); 129 int rockchip_soc_cores_pwr_dm_resume(void); 130 void __dead2 rockchip_soc_soft_reset(void); 131 void __dead2 rockchip_soc_system_off(void); 132 void rockchip_soc_cores_pd_pwr_dn_wfi( 133 const psci_power_state_t *target_state); 134 void rockchip_soc_sys_pd_pwr_dn_wfi(void); 135 136 extern const unsigned char rockchip_power_domain_tree_desc[]; 137 138 extern void *pmu_cpuson_entrypoint; 139 extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 140 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 141 extern const mmap_region_t plat_rk_mmap[]; 142 143 uint32_t rockchip_get_uart_base(void); 144 uint32_t rockchip_get_uart_baudrate(void); 145 uint32_t rockchip_get_uart_clock(void); 146 147 void rockchip_init_scmi_server(void); 148 #endif /* __ASSEMBLER__ */ 149 150 /****************************************************************************** 151 * cpu up status 152 * The bits of macro value is not more than 12 bits for cmp instruction! 153 ******************************************************************************/ 154 #define PMU_CPU_HOTPLUG 0xf00 155 #define PMU_CPU_AUTO_PWRDN 0xf0 156 #define PMU_CLST_RET 0xa5 157 158 #endif /* PLAT_PRIVATE_H */ 159