1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/coreboot.h> 17 #include <lib/mmio.h> 18 #include <plat_private.h> 19 #include <plat/common/platform.h> 20 21 /* 22 * The next 2 constants identify the extents of the code & RO data region. 23 * These addresses are used by the MMU setup code and therefore they must be 24 * page-aligned. It is the responsibility of the linker script to ensure that 25 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 26 */ 27 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); 28 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); 29 30 static entry_point_info_t bl32_ep_info; 31 static entry_point_info_t bl33_ep_info; 32 33 /******************************************************************************* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 ******************************************************************************/ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 entry_point_info_t *next_image_info; 42 43 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 44 45 /* None of the images on this platform can have 0x0 as the entrypoint */ 46 if (next_image_info->pc) 47 return next_image_info; 48 else 49 return NULL; 50 } 51 52 #pragma weak params_early_setup 53 void params_early_setup(void *plat_param_from_bl2) 54 { 55 } 56 57 /******************************************************************************* 58 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 59 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 60 * are lost (potentially). This needs to be done before the MMU is initialized 61 * so that the memory layout can be used while creating page tables. 62 * BL2 has flushed this information to memory, so we are guaranteed to pick up 63 * good data. 64 ******************************************************************************/ 65 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 66 u_register_t arg2, u_register_t arg3) 67 { 68 static console_16550_t console; 69 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0; 70 void *plat_params_from_bl2 = (void *) arg1; 71 72 params_early_setup(plat_params_from_bl2); 73 74 #if COREBOOT 75 if (coreboot_serial.type) 76 console_16550_register(coreboot_serial.baseaddr, 77 coreboot_serial.input_hertz, 78 coreboot_serial.baud, 79 &console); 80 #else 81 console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 82 PLAT_RK_UART_BAUDRATE, &console); 83 #endif 84 85 VERBOSE("bl31_setup\n"); 86 87 /* Passing a NULL context is a critical programming error */ 88 assert(arg_from_bl2); 89 90 assert(arg_from_bl2->h.type == PARAM_BL31); 91 assert(arg_from_bl2->h.version >= VERSION_1); 92 93 bl32_ep_info = *arg_from_bl2->bl32_ep_info; 94 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 95 } 96 97 /******************************************************************************* 98 * Perform any BL3-1 platform setup code 99 ******************************************************************************/ 100 void bl31_platform_setup(void) 101 { 102 generic_delay_timer_init(); 103 plat_rockchip_soc_init(); 104 105 /* Initialize the gic cpu and distributor interfaces */ 106 plat_rockchip_gic_driver_init(); 107 plat_rockchip_gic_init(); 108 plat_rockchip_pmu_init(); 109 } 110 111 /******************************************************************************* 112 * Perform the very early platform specific architectural setup here. At the 113 * moment this is only intializes the mmu in a quick and dirty way. 114 ******************************************************************************/ 115 void bl31_plat_arch_setup(void) 116 { 117 plat_cci_init(); 118 plat_cci_enable(); 119 plat_configure_mmu_el3(BL31_RO_BASE, 120 BL_COHERENT_RAM_END - BL31_RO_BASE, 121 BL31_RO_BASE, 122 BL31_RO_LIMIT, 123 BL_COHERENT_RAM_BASE, 124 BL_COHERENT_RAM_END); 125 } 126