1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm_gic.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <console.h> 35 #include <debug.h> 36 #include <mmio.h> 37 #include <platform.h> 38 #include <plat_private.h> 39 #include <platform_def.h> 40 41 /******************************************************************************* 42 * Declarations of linker defined symbols which will help us find the layout 43 * of trusted SRAM 44 ******************************************************************************/ 45 unsigned long __RO_START__; 46 unsigned long __RO_END__; 47 48 unsigned long __COHERENT_RAM_START__; 49 unsigned long __COHERENT_RAM_END__; 50 51 /* 52 * The next 2 constants identify the extents of the code & RO data region. 53 * These addresses are used by the MMU setup code and therefore they must be 54 * page-aligned. It is the responsibility of the linker script to ensure that 55 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 56 */ 57 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 58 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 59 60 /* 61 * The next 2 constants identify the extents of the coherent memory region. 62 * These addresses are used by the MMU setup code and therefore they must be 63 * page-aligned. It is the responsibility of the linker script to ensure that 64 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 65 * refer to page-aligned addresses. 66 */ 67 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 68 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 69 70 static entry_point_info_t bl32_ep_info; 71 static entry_point_info_t bl33_ep_info; 72 73 /******************************************************************************* 74 * Return a pointer to the 'entry_point_info' structure of the next image for 75 * the security state specified. BL33 corresponds to the non-secure image type 76 * while BL32 corresponds to the secure image type. A NULL pointer is returned 77 * if the image does not exist. 78 ******************************************************************************/ 79 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 80 { 81 entry_point_info_t *next_image_info; 82 83 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 84 85 /* None of the images on this platform can have 0x0 as the entrypoint */ 86 if (next_image_info->pc) 87 return next_image_info; 88 else 89 return NULL; 90 } 91 92 /******************************************************************************* 93 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 94 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 95 * are lost (potentially). This needs to be done before the MMU is initialized 96 * so that the memory layout can be used while creating page tables. 97 * BL2 has flushed this information to memory, so we are guaranteed to pick up 98 * good data. 99 ******************************************************************************/ 100 void bl31_early_platform_setup(bl31_params_t *from_bl2, 101 void *plat_params_from_bl2) 102 { 103 console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 104 PLAT_RK_UART_BAUDRATE); 105 106 VERBOSE("bl31_setup\n"); 107 108 /* Passing a NULL context is a critical programming error */ 109 assert(from_bl2); 110 111 assert(from_bl2->h.type == PARAM_BL31); 112 assert(from_bl2->h.version >= VERSION_1); 113 114 bl32_ep_info = *from_bl2->bl32_ep_info; 115 bl33_ep_info = *from_bl2->bl33_ep_info; 116 117 /* 118 * The code for resuming cpu from suspend must be excuted in pmusram. 119 * Copy the code into pmusram. 120 */ 121 plat_rockchip_pmusram_prepare(); 122 } 123 124 /******************************************************************************* 125 * Perform any BL3-1 platform setup code 126 ******************************************************************************/ 127 void bl31_platform_setup(void) 128 { 129 plat_delay_timer_init(); 130 plat_rockchip_soc_init(); 131 132 /* Initialize the gic cpu and distributor interfaces */ 133 plat_rockchip_gic_driver_init(); 134 plat_rockchip_gic_init(); 135 plat_rockchip_pmu_init(); 136 } 137 138 /******************************************************************************* 139 * Perform the very early platform specific architectural setup here. At the 140 * moment this is only intializes the mmu in a quick and dirty way. 141 ******************************************************************************/ 142 void bl31_plat_arch_setup(void) 143 { 144 plat_cci_init(); 145 plat_cci_enable(); 146 plat_configure_mmu_el3(BL31_RO_BASE, 147 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 148 BL31_RO_BASE, 149 BL31_RO_LIMIT, 150 BL31_COHERENT_RAM_BASE, 151 BL31_COHERENT_RAM_LIMIT); 152 } 153