1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_gic.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <coreboot.h> 12 #include <debug.h> 13 #include <generic_delay_timer.h> 14 #include <mmio.h> 15 #include <plat_private.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <uart_16550.h> 19 20 /* 21 * The next 2 constants identify the extents of the code & RO data region. 22 * These addresses are used by the MMU setup code and therefore they must be 23 * page-aligned. It is the responsibility of the linker script to ensure that 24 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 25 */ 26 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); 27 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); 28 29 static entry_point_info_t bl32_ep_info; 30 static entry_point_info_t bl33_ep_info; 31 32 /******************************************************************************* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 ******************************************************************************/ 38 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 entry_point_info_t *next_image_info; 41 42 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 43 44 /* None of the images on this platform can have 0x0 as the entrypoint */ 45 if (next_image_info->pc) 46 return next_image_info; 47 else 48 return NULL; 49 } 50 51 #pragma weak params_early_setup 52 void params_early_setup(void *plat_param_from_bl2) 53 { 54 } 55 56 /******************************************************************************* 57 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 58 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 59 * are lost (potentially). This needs to be done before the MMU is initialized 60 * so that the memory layout can be used while creating page tables. 61 * BL2 has flushed this information to memory, so we are guaranteed to pick up 62 * good data. 63 ******************************************************************************/ 64 void bl31_early_platform_setup(bl31_params_t *from_bl2, 65 void *plat_params_from_bl2) 66 { 67 static console_16550_t console; 68 69 params_early_setup(plat_params_from_bl2); 70 71 #if COREBOOT 72 if (coreboot_serial.type) 73 console_16550_register(coreboot_serial.baseaddr, 74 coreboot_serial.input_hertz, 75 coreboot_serial.baud, 76 &console); 77 #else 78 console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 79 PLAT_RK_UART_BAUDRATE, &console); 80 #endif 81 82 VERBOSE("bl31_setup\n"); 83 84 /* Passing a NULL context is a critical programming error */ 85 assert(from_bl2); 86 87 assert(from_bl2->h.type == PARAM_BL31); 88 assert(from_bl2->h.version >= VERSION_1); 89 90 bl32_ep_info = *from_bl2->bl32_ep_info; 91 bl33_ep_info = *from_bl2->bl33_ep_info; 92 } 93 94 /******************************************************************************* 95 * Perform any BL3-1 platform setup code 96 ******************************************************************************/ 97 void bl31_platform_setup(void) 98 { 99 generic_delay_timer_init(); 100 plat_rockchip_soc_init(); 101 102 /* Initialize the gic cpu and distributor interfaces */ 103 plat_rockchip_gic_driver_init(); 104 plat_rockchip_gic_init(); 105 plat_rockchip_pmu_init(); 106 } 107 108 /******************************************************************************* 109 * Perform the very early platform specific architectural setup here. At the 110 * moment this is only intializes the mmu in a quick and dirty way. 111 ******************************************************************************/ 112 void bl31_plat_arch_setup(void) 113 { 114 plat_cci_init(); 115 plat_cci_enable(); 116 plat_configure_mmu_el3(BL31_RO_BASE, 117 BL_COHERENT_RAM_END - BL31_RO_BASE, 118 BL31_RO_BASE, 119 BL31_RO_LIMIT, 120 BL_COHERENT_RAM_BASE, 121 BL_COHERENT_RAM_END); 122 } 123